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march 2005 1 m9999-033105 mic2592b mic2592b dual-slot pci express hot-plug controller general description the mic2592b is a dual-slot power controller supporting the power distribution requirements for peripheral component interconnect express (pci express) hot-plug compliant systems. the mic2592b provides complete power control support for two pci express slots, including the 3.3vaux de? ned by the pci express standards. support for 12v, 3.3v, and 3.3vaux supplies is provided including programmable constant-current inrush limiting, voltage supervision, pro- grammable current limit, and circuit breaker functions. these features provide comprehensive system protection and fault isolation. the mic2592b also incorporates an smbus interface via which complete status of each slot is provided. all support documentation can be found on micrels web site at www.micrel.com. micrel, inc. ? 1849 fortune drive ? san jose, ca 95131 ? usa ? tel + 1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com features ? supports two independent pci express slots ? smbus interface for slot power control and status ? voltage-tolerant i/o for compatibility with smbus 2.0 systems ? 12v, 3.3v, and 3.3vaux supplies supported per pci express speci? cation v1.0a - intergrated power mosfets for 3.3v aux - intergrated power mosfets for 3.3v aux - intergrated power mosfets for 3.3v rails - standby operation for wake-on-lan applications with low backfeed on main +12v and +3.3v rails. ? programmable inrush current limiting ? active current regulation controls inrush current ? electronic circuit breaker for each supply to each slot ? high accuracies for both circuit breaker trip points and nuisance trip prevention timers ? dual level fault detection for quick fault response without nuisance tripping ? thermal isolation between circuitry for slot a and slot b ? two general purpose input pins suitable for interface to logic and switches. ordering information part number 12v and 3v 3.3vaux package standard pb-free fast-trip thresholds current limit mic2592b C 2btq mic2592b C 2ytq 100mv 0.375a 48 pin tqfp mic2592b C 3btq* mic2592b C 3ytq* 150mv 0.375a 48 pin tqfp mic2592b C 5btq* mic2592b C 5ytq* disabled 0.375a 48 pin tqfp * contact factory for availability standard pb-free fast-trip thresholds current limit mic2592b C 2btq mic2592b C 2ytq 100mv 0.375a 48 pin tqfp mic2592b C 3btq* mic2592b C 3ytq* 150mv 0.375a 48 pin tqfp mic2592b C 5btq* mic2592b C 5ytq* disabled 0.375a 48 pin tqfp part number 12v and 3v 3.3vaux package standard pb-free fast-trip thresholds current limit mic2592b C 2btq mic2592b C 2ytq 100mv 0.375a 48 pin tqfp mic2592b C 3btq* mic2592b C 3ytq* 150mv 0.375a 48 pin tqfp mic2592b C 5btq* mic2592b C 5ytq* disabled 0.375a 48 pin tqfp part number 12v and 3v 3.3vaux package mic2592b C 2btq mic2592b C 2ytq 100mv 0.375a 48 pin tqfp mic2592b C 3btq* mic2592b C 3ytq* 150mv 0.375a 48 pin tqfp mic2592b C 5btq* mic2592b C 5ytq* disabled 0.375a 48 pin tqfp part number 12v and 3v 3.3vaux package standard pb-free fast-trip thresholds current limit mic2592b C 2btq mic2592b C 2ytq 100mv 0.375a 48 pin tqfp mic2592b C 3btq* mic2592b C 3ytq* 150mv 0.375a 48 pin tqfp mic2592b C 5btq* mic2592b C 5ytq* disabled 0.375a 48 pin tqfp part number 12v and 3v 3.3vaux package part number 12v and 3v 3.3vaux package
mic2592b micrel march 2005 2 m9999-033105 typical application system power supply pci express connector +12v +3.3v vstby vstbyb vstbya vauxa 12vina 12vsensea 3vina 3vsensea 12vinb 12vsenseb 3vinb 3vsenseb 12vgatea 12vouta 3vgatea 3vouta 3vgateb 3voutb vauxb gnd gnd a1 a2 a0 onb ona gpi_b0 gpi_a0 /force_onb /force_ona auxenb auxena /int scl sda 12vgateb 12voutb rfilter[a&b] cfiltera cfilterb mic2592b # c gs 22nf *r 12vgatea 15 ? si4435dy si4420dy # c gate 22nf # c miller 6800pf 15 ? r sense 0.020 ? pci express bus 3.3aux 375ma 3.3v 3.0a 12v 2.1a (x4/x8) r sense 0.020 ? # c gs 22nf *r 12vgateb 15 ? si4435dy # c miller 6800pf r sense 0.013 ? si4420dy # c gate 22nf *r 3vgateb r sense 0.013 ? pci express connector pci express bus 3.3aux 375ma 3.3v 3.0a 12v 2.1a (x4/x8) * values for r 12vgate[a/b] and r 3vgate[a/b] may vary depending upon the c gs of the external mosfets. # these components are not required for mic2592b operation but can be implemented for gate output slew rate control (application specific) bold lines indicate high current paths 4 9 2 11 26 5 8 3 10 12 13 14 16 32 29 34 27 25 24 23 21 22 17 gnd 33 46 15 15 ? *r 3vgatea 0.1f 0.1f 0.1 ? f 0.1 ? f 0.1 ? f 0.1 ? f /faultb /faulta /pwrgdb /pwrgda 1 onb ona auxenb auxena /int scl sda 110k ? 1% hot-plug controller smbus i/o management controller 48 47 37 43 42 38 28 35 20 45 44 v stby c1 c2 v stby 10k x 3 10k x 4 sda scl /int smbus base address 39 40 41 gpi_b0 100k 100k 100k 100k gpi_a0 v stby /force_onb /force_ona /faultb /faulta /pwrgdb /pwrgda 36 31 6 v stby 10k x 4
march 2005 3 m9999-033105 mic2592b micrel pin con? guration 48-pin tqfp gnd 3vouta vauxa 3vgatea 3vsensea nc nc rfilter[a&b] /faulta cfiltera 12vgatea gpi_a0 12vina /pwrgda nc 12vsensea 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 /force_ona 12vouta vstbya 3vina 9 10 11 12 3voutb vauxb 3vgateb 3vsenseb 21 22 23 24 /faultb cfilterb 12vgateb gnd 12vinb /pwrgdb nc 12vsenseb 36 35 34 33 32 31 30 29 /force_onb 12voutb vstbyb 3vinb 28 27 26 25 ona auxena gnd scl sda onb auxenb a0 48 47 46 45 44 43 42 41 a1 a2 gpi_b0 /int 40 39 38 37 hot-plug control interface slot a interface slot b interface
mic2592b micrel march 2005 4 m9999-033105 pin description pin number pin name pin function 5 12vina 12v supply power and sense inputs [a/b]: two pins are provided for kelvin. 32 12vinb connection (one for each slot). pin 5 is the (+) kelvin-sense connection to the supply side of the sense resistor for 12v slot a. pin 32 is the (+) kelvin sense connection to the supply side of the sense resistor for 12v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 12 3vina 3.3v supply power and sense inputs [a/b]: two pins are provided for 25 3vinb connection (one for each slot). pin 12 is the (+) kelvin-sense connection to the supply side of the sense resistor for 3v slot a. pin 25 is the (+) kelvin sense connection to the supply side of the sense resistor for 3v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 16 3vouta 3.3v power-good sense inputs: connect to 3.3v[a/b] outputs. used to 21 3voutb monitor the 3.3v output voltages for power-is-good status. 10 12vouta 12v power-good sense inputs: connect to 12v[a/b] outputs. used to 27 12voutb monitor the 12v output voltages for power-is-good status. 8 12vsensea 12v circuit breaker sense inputs: the current limit thresholds are set 29 12vsenseb by connecting sense resistors between these pins and 12vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 12vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t flt , the circuit breaker is tripped and the gate pin for the affected 12v flt , the circuit breaker is tripped and the ga te pin for the af fected 12v flt supplys external mosfet is immediately pulled high. 13 3vsensea 3v circuit breaker sense inputs: the current limit thresholds are set by 24 3vsenseb connecting sense resistors between these pins and 3vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 3vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t flt , the circuit breaker is tripped and the gate pin for the affected 3v flt , the circuit breaker is tripped and the ga te pin for the af fected 3v flt supplys external mosfet is immediately pulled low. 3 12vgatea 12v gate drive outputs: each pin connects to the gate of an external 34 12vgateb p-channel mosfet. during power-up, the c gate and the c gs of the mosfets are connected to a 25a current sink. this controls the value of dv/dt seen at the source of the mosfets. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t flt . whenever an flt . whenever an flt overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought high. these pins are charged by an internal current source during power-down. also, the 3v supply for the affected slot is shut-down. 14 3vgatea 3v gate drive outputs: each pin connects to the gate of an external 23 3vgateb n-channel mosfet. during power-up, the c gate and the c gs of the mosfets are connected to a 25a current source. this controls the value of dv/dt seen at the source of the mosfets, and hence the current ? owing into the load capacitance. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t flt . whenever an flt . whenever an flt overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought low. during power- down, these pins are discharged by an internal current source. also, the 12v supply for the affected slot is shut down. pin number pin name pin function 32 12vinb connection (one for each slot). pin 5 is the (+) kelvin-sense connection to the supply side of the sense resistor for 12v slot a. pin 32 is the (+) kelvin sense connection to the supply side of the sense resistor for 12v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 12 3vina 3.3v supply power and sense inputs [a/b]: two pins are provided for 25 3vinb connection (one for each slot). pin 12 is the (+) kelvin-sense connection to the supply side of the sense resistor for 3v slot a. pin 25 is the (+) kelvin sense connection to the supply side of the sense resistor for 3v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 16 3vouta 3.3v power-good sense inputs: connect to 3.3v[a/b] outputs. used to 21 3voutb monitor the 3.3v output voltages for power-is-good status. 10 12vouta 12v power-good sense inputs: connect to 12v[a/b] outputs. used to 27 12voutb monitor the 12v output voltages for power-is-good status. 8 12vsensea 12v circuit breaker sense inputs: the current limit thresholds are set 29 12vsenseb by connecting sense resistors between these pins and 12vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 12vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t supplys external mosfet is immediately pulled high. 13 3vsensea 3v circuit breaker sense inputs: the current limit thresholds are set by 24 3vsenseb connecting sense resistors between these pins and 3vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 3vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t supplys external mosfet is immediately pulled low. 3 12vgatea 12v gate drive outputs: each pin connects to the gate of an external 34 12vgateb p-channel mosfet. during power-up, the c mosfets are connected to a 25a current sink. this controls the value of dv/dt seen at the source of the mosfets. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought high. these pins are charged by an internal current source during power-down. also, the 3v supply for the affected slot is shut-down. 14 3vgatea 3v gate drive outputs: each pin connects to the gate of an external 23 3vgateb n-channel mosfet. during power-up, the c mosfets are connected to a 25a current source. this controls the value of dv/dt seen at the source of the mosfets, and hence the current ? owing into the load capacitance. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought low. during power- down, these pins are discharged by an internal current source. also, the 12v supply for the affected slot is shut down. pin number pin name pin function 5 12vina 12v supply power and sense inputs [a/b]: two pins are provided for kelvin. 32 12vinb connection (one for each slot). pin 5 is the (+) kelvin-sense connection to the supply side of the sense resistor for 12v slot a. pin 32 is the (+) kelvin sense connection to the supply side of the sense resistor for 12v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 12 3vina 3.3v supply power and sense inputs [a/b]: two pins are provided for 25 3vinb connection (one for each slot). pin 12 is the (+) kelvin-sense connection to the supply side of the sense resistor for 3v slot a. pin 25 is the (+) kelvin sense connection to the supply side of the sense resistor for 3v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 16 3vouta 3.3v power-good sense inputs: connect to 3.3v[a/b] outputs. used to 21 3voutb monitor the 3.3v output voltages for power-is-good status. 10 12vouta 12v power-good sense inputs: connect to 12v[a/b] outputs. used to 27 12voutb monitor the 12v output voltages for power-is-good status. 8 12vsensea 12v circuit breaker sense inputs: the current limit thresholds are set 29 12vsenseb by connecting sense resistors between these pins and 12vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 12vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t supplys external mosfet is immediately pulled high. 13 3vsensea 3v circuit breaker sense inputs: the current limit thresholds are set by 24 3vsenseb connecting sense resistors between these pins and 3vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 3vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t supplys external mosfet is immediately pulled low. 3 12vgatea 12v gate drive outputs: each pin connects to the gate of an external 34 12vgateb p-channel mosfet. during power-up, the c mosfets are connected to a 25a current sink. this controls the value of dv/dt seen at the source of the mosfets. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought high. these pins are charged by an internal current source during power-down. also, the 3v supply for the affected slot is shut-down. 14 3vgatea 3v gate drive outputs: each pin connects to the gate of an external 23 3vgateb n-channel mosfet. during power-up, the c mosfets are connected to a 25a current source. this controls the value of dv/dt seen at the source of the mosfets, and hence the current ? owing into the load capacitance. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought low. during power- down, these pins are discharged by an internal current source. also, the 12v supply for the affected slot is shut down. pin number pin name pin function 5 12vina 12v supply power and sense inputs [a/b]: two pins are provided for kelvin. 32 12vinb connection (one for each slot). pin 5 is the (+) kelvin-sense connection to the supply side of the sense resistor for 12v slot a. pin 32 is the (+) kelvin sense connection to the supply side of the sense resistor for 12v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 12 3vina 3.3v supply power and sense inputs [a/b]: two pins are provided for 25 3vinb connection (one for each slot). pin 12 is the (+) kelvin-sense connection to the supply side of the sense resistor for 3v slot a. pin 25 is the (+) kelvin sense connection to the supply side of the sense resistor for 3v slot b. these two pins must ultimately connect to each other as close as possible at the mic2592b controller in order to eliminate any ir drop between these pins. an undervoltage lockout circuit (uvlo) prevents the switches from turning on while this input is less than its lockout threshold. 16 3vouta 3.3v power-good sense inputs: connect to 3.3v[a/b] outputs. used to 21 3voutb monitor the 3.3v output voltages for power-is-good status. 10 12vouta 12v power-good sense inputs: connect to 12v[a/b] outputs. used to 27 12voutb monitor the 12v output voltages for power-is-good status. 8 12vsensea 12v circuit breaker sense inputs: the current limit thresholds are set 29 12vsenseb by connecting sense resistors between these pins and 12vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 12vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t supplys external mosfet is immediately pulled high. 13 3vsensea 3v circuit breaker sense inputs: the current limit thresholds are set by 24 3vsenseb connecting sense resistors between these pins and 3vin[a/b]. when the current limit threshold of ir = 50mv is reached, the 3vgate[a/b] pin is modulated to maintain a constant voltage across the sense resistor and therefore a constant current into the load. if the 50mv threshold is exceeded for t supplys external mosfet is immediately pulled low. 3 12vgatea 12v gate drive outputs: each pin connects to the gate of an external 34 12vgateb p-channel mosfet. during power-up, the c mosfets are connected to a 25a current sink. this controls the value of dv/dt seen at the source of the mosfets. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought high. these pins are charged by an internal current source during power-down. also, the 3v supply for the affected slot is shut-down. 14 3vgatea 3v gate drive outputs: each pin connects to the gate of an external 23 3vgateb n-channel mosfet. during power-up, the c mosfets are connected to a 25a current source. this controls the value of dv/dt seen at the source of the mosfets, and hence the current ? owing into the load capacitance. during current limit events, the voltage at this pin is adjusted to maintain constant current through the switch for a period of t overcurrent, thermal shutdown, or input undervoltage fault condition occurs, the gate pin for the affected slot is immediately brought low. during power- down, these pins are discharged by an internal current source. also, the 12v supply for the affected slot is shut down.
march 2005 5 m9999-033105 mic2592b micrel pin description (continued) pin number pin name pin function 11 vstbya 3.3v standby input voltage: required to support pci express vaux output. 26 vstbyb additionally, the smbus logic and internal registers run off of vstby[a/b] to ensure that the chip is accessible during standby modes. a uvlo circuit prevents turn-on of this supply until vstby[a/b] rises above its uvlo threshold. both pins must be externally connected together at the mic2592b controller. 15 vauxa 3.3vaux[a/b] outputs to pci express card slots: these outputs connect 22 vauxb the 3.3a ux pin of the pci express connectors to vstby[a/b] via internal 400m mosfets. these outputs are current limited and protected against short-circuit faults. 44 ona enable inputs: rising-edge triggered. used to enable or disable the maina 43 onb and mainb (+3.3v and +12v) outputs. the outputs can be switched on by these controls only after the v stby input supply is valid and stabe (i.e., t stby input supply is valid and stabe (i.e., t stby por elapses - see the electrical characteristics table). taking on[a/b] low after a fault resets the +12v and/or +3.3v fault latches for the affected slot. tie these pins to gnd if using smi power control. also, see pin description for /faulta and /faultb. 45 auxena enable inputs: rising-edge triggered. used to enable or disable the 42 auxenb vaux[a/b] outputs. the outputs can be switched on by these controls only after the v stby input supply is valid and stabe (i.e., t stby input supply is valid and stabe (i.e., t stby por elapses - see the electrical characteristics table). taking auxen[a/b] low after a fault resets the respective slots aux output fault latch. tie these pins to gnd if using smi power c ontrol. also, see pin description for /faulta an d /faultb. 2 cfiltera overcurrent timers: capacitors connected between these 35 cfilterb pins and gnd set the duration of t flt for each slot. the overcurrent ? lter delay (t flt ) is the amount of time for which a slot remains in current limit before its circuit breaker is tripped. 6 /pwrgda /pwrgd[a/b] outputs: open-drain, active-low. asserted when a slot has 31 /pwrgdb been commanded to turn on and has successfully begun delivering power to its respective +12v, +3.3v, and vaux outputs. each pin requires an extern al pull-up resistor to v stby . stby . stby 1 /faulta /fault[a/b] outputs: open-drain, active-low. asserted whenever the 36 /faultb circuit br eaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). each pin requires an external pull-up resistor to v stby . stby . stby bringing the slots on[a/b] pin low resets /fault[a/b] if /fault[a/b] was ass erted in response to a fault condition on one of the slots main out- puts (+12v or +3.3v). /fault[a/b] is reset by bringing the slots auxen[a/b] pin low if /fault[a/b] was asserted in response to a fault condition on the slots vaux output. if a fault condition occurred on both the main and vaux outputs of the same slot, then both on[a/b] and auxen[a/b] must be brought low to deassert the /fault[a/b] output. 9 /force_ona enable inputs: active-low, level-sensitive. asserting a /force_on[a/b] 28 /force_onb input will turn on all three of the respective slots outputs (+12v, +3.3v, and vaux), while speci? cally defeating all protections on those supplies. this explcitly includes all overcurrent and short circuit protections, and on-chip thermal protection for the vaux[a/b] supplies. additionally included are the uvlo protections for the +3.3v and +12v main supplies. the /force_on[a/b] pins do not disable uvlo protection for the vaux[a/b] supplies. these input pins are intended for diagnostic purposes only. asserting /force_on[a/b] will cause the respective slots /pwrgd[a/b] and /fault[a/b] pins to enter their open-drain state. note that the smbus register set will continue to re? ect the actual state of each slots supplies. there is a pair of register bits, accessible via the smbus, which can be set to disable (unconditionally deassert) either or both of the /force_on[a/b] pins -- see cntrl[a/b] register bit d[2]. 4 gpi_a0 general purpose inputs: the states of these two inputs are available by 38 gpi_b0 reading the common status register, bits [4:5]. if not used, connect each pin to gnd. pin number pin name pin function 26 vstbyb additionally, the smbus logic and internal registers run off of vstby[a/b] to ensure that the chip is accessible during standby modes. a uvlo circuit prevents turn-on of this supply until vstby[a/b] rises above its uvlo threshold. both pins must be externally connected together at the mic2592b controller. 15 vauxa 3.3vaux[a/b] outputs to pci express card slots: these outputs connect 22 vauxb the 3.3a ux pin of the pci express connectors to vstby[a/b] via internal 400m mosfets. these outputs are current limited and protected against short-circuit faults. 44 ona enable inputs: rising-edge triggered. used to enable or disable the maina 43 onb and mainb (+3.3v and +12v) outputs. the outputs can be switched on by these controls only after the v elapses - see the electrical characteristics table). taking on[a/b] low after a fault resets the +12v and/or +3.3v fault latches for the affected slot. tie these pins to gnd if using smi power control. also, see pin description for /faulta and /faultb. 45 auxena enable inputs: rising-edge triggered. used to enable or disable the 42 auxenb vaux[a/b] outputs. the outputs can be switched on by these controls only after the v electrical characteristics table). taking auxen[a/b] low after a fault resets the respective slots aux output fault latch. tie these pins to gnd if using smi power 2 cfiltera overcurrent timers: capacitors connected between these 35 cfilterb pins and gnd set the duration of t delay (t before its circuit breaker is tripped. 31 /pwrgdb been commanded to turn on and has successfully begun delivering power to its respective +12v, +3.3v, and vaux outputs. each pin requires an extern pull-up resistor to v 1 /faulta /fault[a/b] outputs: open-drain, active-low. asserted whenever the 36 /faultb circuit br eaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). each pin requires an external pull-up resistor to v bringing the slots on[a/b] pin low resets /fault[a/b] if /fault[a/b] was ass erted in response to a fault condition on one of the slots main out- puts (+12v or +3.3v). /fault[a/b] is reset by bringing the slots auxen[a/b] pin low if /fault[a/b] was asserted in response to a fault condition on the slots vaux output. if a fault condition occurred on both the main and vaux outputs of the same slot, then both on[a/b] and auxen[a/b] must be brought low to deassert the /fault[a/b] output. 9 /force_ona enable inputs: active-low, level-sensitive. asserting a /force_on[a/b] 28 /force_onb input will turn on all three of the respective slots outputs (+12v, +3.3v, and vaux), while speci? cally defeating all protections on those supplies. this explcitly includes all overcurrent and short circuit protections, and on-chip uvlo protections for the +3.3v and +12v main supplies. the /force_on[a/b] pins do supplies. these input pins are intended for diagnostic purposes only. asserting /force_on[a/b] will cause the respective slots /pwrgd[a/b] and /fault[a/b] pins to enter their open-drain state. note that the smbus register set will continue to re? ect the actual state of each slots supplies. there is a pair of register bits, accessible via the smbus, which can be set to disable (unconditionally deassert) either or both of the /force_on[a/b] pins -- see cntrl[a/b] register bit d[2]. 4 gpi_a0 general purpose inputs: the states of these two inputs are available by pin to gnd. pin number pin name pin function 11 vstbya 3.3v standby input voltage: required to support pci express vaux output. 26 vstbyb additionally, the smbus logic and internal registers run off of vstby[a/b] to ensure that the chip is accessible during standby modes. a uvlo circuit prevents turn-on of this supply until vstby[a/b] rises above its uvlo threshold. both pins must be externally connected together at the mic2592b controller. 15 vauxa 3.3vaux[a/b] outputs to pci express card slots: these outputs connect 22 vauxb the 3.3a ux pin of the pci express connectors to vstby[a/b] via internal 400m mosfets. these outputs are current limited and protected against short-circuit faults. 44 ona enable inputs: rising-edge triggered. used to enable or disable the maina 43 onb and mainb (+3.3v and +12v) outputs. the outputs can be switched on by these controls only after the v elapses - see the electrical characteristics table). taking on[a/b] low after a fault resets the +12v and/or +3.3v fault latches for the affected slot. tie these pins to gnd if using smi power control. also, see pin description for /faulta and /faultb. 45 auxena enable inputs: rising-edge triggered. used to enable or disable the 42 auxenb vaux[a/b] outputs. the outputs can be switched on by these controls only after the v electrical characteristics table). taking auxen[a/b] low after a fault resets the respective slots aux output fault latch. tie these pins to gnd if using smi power 2 cfiltera overcurrent timers: capacitors connected between these 35 cfilterb pins and gnd set the duration of t delay (t before its circuit breaker is tripped. 6 /pwrgda /pwrgd[a/b] outputs: open-drain, active-low. asserted when a slot has 31 /pwrgdb been commanded to turn on and has successfully begun delivering power to its respective +12v, +3.3v, and vaux outputs. each pin requires an extern pull-up resistor to v 1 /faulta /fault[a/b] outputs: open-drain, active-low. asserted whenever the 36 /faultb circuit br eaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). each pin requires an external pull-up resistor to v bringing the slots on[a/b] pin low resets /fault[a/b] if /fault[a/b] was ass erted in response to a fault condition on one of the slots main out- puts (+12v or +3.3v). /fault[a/b] is reset by bringing the slots auxen[a/b] pin low if /fault[a/b] was asserted in response to a fault condition on the slots vaux output. if a fault condition occurred on both the main and vaux outputs of the same slot, then both on[a/b] and auxen[a/b] must be brought low to deassert the /fault[a/b] output. 9 /force_ona enable inputs: active-low, level-sensitive. asserting a /force_on[a/b] 28 /force_onb input will turn on all three of the respective slots outputs (+12v, +3.3v, and vaux), while speci? cally defeating all protections on those supplies. this explcitly includes all overcurrent and short circuit protections, and on-chip uvlo protections for the +3.3v and +12v main supplies. the /force_on[a/b] pins do supplies. these input pins are intended for diagnostic purposes only. asserting /force_on[a/b] will cause the respective slots /pwrgd[a/b] and /fault[a/b] pins to enter their open-drain state. note that the smbus register set will continue to re? ect the actual state of each slots supplies. there is a pair of register bits, accessible via the smbus, which can be set to disable (unconditionally deassert) either or both of the /force_on[a/b] pins -- see cntrl[a/b] register bit d[2]. 4 gpi_a0 general purpose inputs: the states of these two inputs are available by 38 gpi_b0 reading the common status register, bits [4:5]. if not used, connect each pin to gnd. pin number pin name pin function 11 vstbya 3.3v standby input voltage: required to support pci express vaux output. 26 vstbyb additionally, the smbus logic and internal registers run off of vstby[a/b] to ensure that the chip is accessible during standby modes. a uvlo circuit prevents turn-on of this supply until vstby[a/b] rises above its uvlo threshold. both pins must be externally connected together at the mic2592b controller. 15 vauxa 3.3vaux[a/b] outputs to pci express card slots: these outputs connect 22 vauxb the 3.3a ux pin of the pci express connectors to vstby[a/b] via internal 400m mosfets. these outputs are current limited and protected against short-circuit faults. 44 ona enable inputs: rising-edge triggered. used to enable or disable the maina 43 onb and mainb (+3.3v and +12v) outputs. the outputs can be switched on by these controls only after the v elapses - see the electrical characteristics table). taking on[a/b] low after a fault resets the +12v and/or +3.3v fault latches for the affected slot. tie these pins to gnd if using smi power control. also, see pin description for /faulta and /faultb. 45 auxena enable inputs: rising-edge triggered. used to enable or disable the 42 auxenb vaux[a/b] outputs. the outputs can be switched on by these controls only after the v electrical characteristics table). taking auxen[a/b] low after a fault resets the respective slots aux output fault latch. tie these pins to gnd if using smi power 2 cfiltera overcurrent timers: capacitors connected between these 35 cfilterb pins and gnd set the duration of t delay (t before its circuit breaker is tripped. 6 /pwrgda /pwrgd[a/b] outputs: open-drain, active-low. asserted when a slot has 31 /pwrgdb been commanded to turn on and has successfully begun delivering power to its respective +12v, +3.3v, and vaux outputs. each pin requires an extern pull-up resistor to v 1 /faulta /fault[a/b] outputs: open-drain, active-low. asserted whenever the 36 /faultb circuit br eaker trips due to a fault condition (overcurrent, input undervoltage, overtemperature). each pin requires an external pull-up resistor to v bringing the slots on[a/b] pin low resets /fault[a/b] if /fault[a/b] was ass erted in response to a fault condition on one of the slots main out- puts (+12v or +3.3v). /fault[a/b] is reset by bringing the slots auxen[a/b] pin low if /fault[a/b] was asserted in response to a fault condition on the slots vaux output. if a fault condition occurred on both the main and vaux outputs of the same slot, then both on[a/b] and auxen[a/b] must be brought low to deassert the /fault[a/b] output. 9 /force_ona enable inputs: active-low, level-sensitive. asserting a /force_on[a/b] 28 /force_onb input will turn on all three of the respective slots outputs (+12v, +3.3v, and vaux), while speci? cally defeating all protections on those supplies. this explcitly includes all overcurrent and short circuit protections, and on-chip uvlo protections for the +3.3v and +12v main supplies. the /force_on[a/b] pins do supplies. these input pins are intended for diagnostic purposes only. asserting /force_on[a/b] will cause the respective slots /pwrgd[a/b] and /fault[a/b] pins to enter their open-drain state. note that the smbus register set will continue to re? ect the actual state of each slots supplies. there is a pair of register bits, accessible via the smbus, which can be set to disable (unconditionally deassert) either or both of the /force_on[a/b] pins -- see cntrl[a/b] register bit d[2]. 4 gpi_a0 general purpose inputs: the states of these two inputs are available by 38 gpi_b0 reading the common status register, bits [4:5]. if not used, connect each pin to gnd.
mic2592b micrel march 2005 6 m9999-033105 pin description (continued) pin number pin name pin function 39 a2 smbus address select pins: connect to ground or leave open in order to 40 a1 program device smbus base address. these inputs have internal pull-up 41 a0 resistors to vstby[a/b]. 48 sda smbus data: bidirectional smbus data line. 47 scl smbus clock: input. 37 /int interrupt output: open-drain, active-low. asserted whenever a power fault is detect ed if the intmsk bit (cs register bit d[3]) is a logical "0". this output is cleared by performing an "echo reset" to the appropriate fault bit(s) in the stat[a/b] and/or cs registers. this pin requires an external pull-up resistor to v stby . stby . stby 17 gnd 3 pins, ic ground connections: tie directly to the systems analog gnd 33 plane directly at the device. 46 20 rfilter[a&b] connecting this pin to gnd through a 110k, 1% resistor will provide a signi? cant improvement in timeout duration accuracy for slow overcurrent faults on slot a and slot b. if left ? oating (nc), overcurrent timeout duration accuracy is determined by the speci? cation for v filter and i filter . please see the circuit breaker function text in the functional description section for more detail. 7 nc reserved: make no external connections to these pins. 18 19 30 40 a1 program device smbus base address. these inputs have internal pull-up 41 a0 resistors to vstby[a/b]. 48 sda smbus data: bidirectional smbus data line. 47 scl smbus clock: input. 37 /int interrupt output: open-drain, active-low. asserted whenever a power fault is detect ed if the intmsk bit (cs register bit d[3]) is a logical "0". this output is cleared by performing an "echo reset" to the appropriate fault bit(s) in the stat[a/b] and/or cs registers. this pin requires an external pull-up resistor to v 17 gnd 3 pins, ic ground connections: tie directly to the systems analog gnd 33 plane directly at the device. 46 20 rfilter[a&b] connecting this pin to gnd through a 110k, 1% resistor will provide a signi? cant improvement in timeout duration accuracy for slow overcurrent faults on slot a and slot b. if left ? oating (nc), overcurrent timeout duration accuracy is determined by the speci? cation for v see the circuit breaker function text in the functional description section for more detail. 7 nc reserved: make no external connections to these pins. 18 19 30 pin number pin name pin function 39 a2 smbus address select pins: connect to ground or leave open in order to 40 a1 program device smbus base address. these inputs have internal pull-up 41 a0 resistors to vstby[a/b]. 48 sda smbus data: bidirectional smbus data line. 47 scl smbus clock: input. 37 /int interrupt output: open-drain, active-low. asserted whenever a power fault is detect ed if the intmsk bit (cs register bit d[3]) is a logical "0". this output is cleared by performing an "echo reset" to the appropriate fault bit(s) in the stat[a/b] and/or cs registers. this pin requires an external pull-up resistor to v 17 gnd 3 pins, ic ground connections: tie directly to the systems analog gnd 33 plane directly at the device. 20 rfilter[a&b] connecting this pin to gnd through a 110k, 1% resistor will provide a signi? cant improvement in timeout duration accuracy for slow overcurrent faults on slot a and slot b. if left ? oating (nc), overcurrent timeout duration accuracy is determined by the speci? cation for v see the circuit breaker function text in the functional description section for more detail. 7 nc reserved: make no external connections to these pins. pin number pin name pin function 39 a2 smbus address select pins: connect to ground or leave open in order to 40 a1 program device smbus base address. these inputs have internal pull-up 41 a0 resistors to vstby[a/b]. 48 sda smbus data: bidirectional smbus data line. 47 scl smbus clock: input. 37 /int interrupt output: open-drain, active-low. asserted whenever a power fault is detect ed if the intmsk bit (cs register bit d[3]) is a logical "0". this output is cleared by performing an "echo reset" to the appropriate fault bit(s) in the stat[a/b] and/or cs registers. this pin requires an external pull-up resistor to v 17 gnd 3 pins, ic ground connections: tie directly to the systems analog gnd 33 plane directly at the device. 20 rfilter[a&b] connecting this pin to gnd through a 110k, 1% resistor will provide a signi? cant improvement in timeout duration accuracy for slow overcurrent faults on slot a and slot b. if left ? oating (nc), overcurrent timeout duration accuracy is determined by the speci? cation for v see the circuit breaker function text in the functional description section for more detail. 7 nc reserved: make no external connections to these pins.
march 2005 7 m9999-033105 mic2592b micrel absolute maximum ratings (1) supply voltages 12vin[a/b] ............................................................... 14v 3vin[a/b], vstby[a/b] ............................................... 7v any logic pin ......................... C0.5v (min) to 3.6v (max) output current (/fault[a/b], /int, sda) ................... 10ma power dissipation ..................................... internally limited lead temperature (ir re? ow, peak temperature) ........ 240c +0c/C5c pb-free package (-xytq) (ir re? ow, peak temperature) ........ 260c +0c/C5c storage temperature ................................ C65c to +150c esd rating ( 3) operating ratings (2) supply voltages 12vin[a/b] ................................................ 11.0v to 13.0v 3vin[a/b] ...................................................... 3.0v to 3.6v vstby[a/b] .................................................. 3.0v to 3.6v ambient temperature (t a ambient temperature (t a ambient temperature (t ) ............................. 0c to + 70c junction temperature (t j ) ......................................... 125c package thermal resistance tqfp ( ja ) ...................................................................... 56.5c/w electrical characteristics (4) 12v in[a/b] = 12v, 3v in[a/b] = 3.3v, v stby[a/b] = 3.3v, t a = 3.3v, t a = 3.3v, t = 25c, unless otherwise noted. a = 25c, unless otherwise noted. a bold indicates speci? cation applies over the full operating temperature range from 0c to +70c. symbol parameter condition min typ max units power control and logic sections i cc12 supply current 2.5 5 ma i cc3.3 0.5 1 ma i ccstby 2.5 ccstby 2.5 ccstby 5 ma undervoltage lockout thresholds v uvlo(12v) 12vin[a/b] 12v in[a/b] increasing 8 9 10 v v uvlo(3v) 3vin[a/b] 3v uvlo(12v) 3vin[a/b] 3v uvlo(12v) in[a/b] increasing 2.2 2.5 2.75 v v uvlo(stby) vstby[a/b] v stby[a/b] increasing 2.8 2.9 3.0 v v hysuv undervoltage lockout hysteresis 180 mv 12v in , 3v in v hysstby undervoltage lockout hysteresis 50 mv hysstby undervoltage lockout hysteresis 50 mv hysstby v stby[a/b] power-good undervoltage thresholds v uvth(12v) 12vout[a/b] 12v out[a/b] decreasing 10.2 10.5 10.8 v v uvth(3v) 3vout[a/b] 3v uvth(12v) 3vout[a/b] 3v uvth(12v) out[a/b] decreasing 2.7 2.8 2.9 v v uvth(vaux) vaux[a/b] v aux[a/b] vaux[a/b] v aux[a/b] vaux[a/b] v decreasing 2.7 2.8 2.9 v v hyspg power-good detect hysteresis 30 mv v gate(12v) 12vgate voltage 0 1.5 v i gate(12vsink) 12vgate sink current start cycle 15 25 35 a i gate(12vpullup) 12vgate pull-up current (fault off) any fault condition C20 ma (v gate(12vpullup) (v gate(12vpullup) dd Cv gate ) = 2.5v v gate(3v) 3vgate voltage 12v in C1.5 12v in v i gate(3vcharge) 3vgate charge current start cycle 15 25 35 a i gate(3vsink) 3vgate sink current (fault off) any fault condition 40 ma v gate = 2.5v cfilter[a/b] overcurrent delay time, pin 20 (rfilter[a&b]) floating or nc v filter cfilter[a/b] threshold voltage 1.20 1.25 1.30 v i filter cfilter[a/b] charging current v 12vin C v 12vsense > v thilimit 1.80 2.5 5.0 a delay ms c f v ( v) i a filter filter filter ? ? ? ? ? ? ? ? ? ? ? 10 3 and/or notes: 1. exceeding measurements given within the absolute maximum ratings section may damage the device. 2. the device is not guaranteed to function outside of the measurements given in the operating ratings" section. 3. devices are esd sensitive. employ proper handling precautions. the human body model is 1.5k in series with 100pf. 4. speci? cation for packaged product only. symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units cfilter[a/b] threshold voltage 1.25 2.5 a cfilter[a/b] threshold voltage charging current v supply current 2.5 0.5 2.5 undervoltage lockout thresholds 12vin[a/b] 12v 3vin[a/b] 3v undervoltage lockout hysteresis 180 mv 12v undervoltage lockout hysteresis 50 mv v 12vout[a/b] 12v 3vout[a/b] 3v power-good detect hysteresis 30 mv 12vgate voltage 12vgate 12vgate pull-up current (fault off) any fault condition (v 3vgate voltage 3vgate charge current start cycle 3vgate sink current (fault off) any fault condition v supply current 2.5 0.5 2.5 undervoltage lockout thresholds 12vin[a/b] 12v 3vin[a/b] 3v vstby[a/b] v undervoltage lockout hysteresis 180 mv undervoltage lockout hysteresis 50 mv 12vout[a/b] 12v 3vout[a/b] 3v vaux[a/b] v power-good detect hysteresis 30 mv 12vgate voltage sink current start cycle 12vgate pull-up current (fault off) any fault condition (v 3vgate voltage 3vgate charge current start cycle 3vgate sink current (fault off) any fault condition v supply current 2.5 0.5 2.5 undervoltage lockout thresholds undervoltage lockout hysteresis 180 mv undervoltage lockout hysteresis 50 mv power-good detect hysteresis 30 mv supply current 2.5 0.5 2.5 undervoltage lockout thresholds 9 2.5 2.9 undervoltage lockout hysteresis 180 mv undervoltage lockout hysteresis 50 mv 10.5 2.8 2.8 power-good detect hysteresis 30 mv 25 ma 25 ma undervoltage lockout thresholds undervoltage lockout hysteresis 180 mv undervoltage lockout hysteresis 50 mv power-good detect hysteresis 30 mv ma ma ma ma ma v v v undervoltage lockout hysteresis 180 mv undervoltage lockout hysteresis 50 mv v v v power-good detect hysteresis 30 mv v a ma v a ma v 3vin C v 3vsense > v thilimit
mic2592b micrel march 2005 8 m9999-033105 electrical characteristics (continued) (5) symbol parameter condition min typ max units c filter overcurrent delaytime, pin 20 grounded through rfilter[a&b] = 110 k, 1% sf c filter overcurrent delay v 12vin C v 12vsense > v thilimit thilimit thilimit scaling factor and/or 4.4 5 5.6 delay(ms)=c filter (f) r filter (k) sf v 3vin Cv 3vsense > v thilimit v thilimit current limit threshold voltages thilimit current limit threshold v oltages thilimit 12v[a/b] supplies v 12vin C v 12vsense 45 50 55 mv 3.3v[a/b] supplies v 3vin C v 3vsense 45 50 55 mv v thfast 12vout[a/b] and 3vout[a/b] v thfast 12vout[a/b] and 3vout[a/b] v thfast 12vin C v 12vsense MIC2592B-2BTQ 90 100 110 mv fast-trip threshold voltages v 3vin C v 3vsense mic2592b-3btq 135 150 165 mv mic2592b-5btq disabled i 12vsense[a/b] 12vsense[a/b] input current 0.35 a i 3vsense[a/b] 3vsense[a/b] input current 0.35 a v il low-level input voltage il low -level input v oltage il C0.5 0.8 v on[a/b], auxen[a/b], gpi_[a0/b0], /force_on[a/b] v ol output low voltage i ol output low v oltage i ol ol = 3ma ol = 3ma ol 0.4 v /fault[a/b], /pwrgd[a/b], /int, sda v ih high-level input voltage 2.1 3.6 v on[a/b], auxen[a/b], gpi_[a0/b0], /force_on[a/b], a[0-2], scl, sda r pullup(a0 - a2) internal pull-ups from a[0-2] to 40 k v stby[a/b] i lkg,off( 12vin[a/b]) 12vin[a/b] input leakage current v stby = vstby[a/b] = +3.3v, 1 a stby = vstby[a/b] = +3.3v , 1 a stby 12vin[a/b] = off; 3vin[a/b] = off lkg,off( 12vin[a/b] = off; 3vin[a/b] = off lkg,off( 12vin[a/b]) 12vin[a/b] = off; 3vin[a/b] = off 12vin[a/b]) i lkg,off( 3vin[a/b]) 3vin[a/b] input leakage current v stby = vstby[a/b] = +3.3v, 1 a stby = vstby[a/b] = +3.3v , 1 a stby 3vin[a/b] = off; 12vin[a/b] = off lkg,off( 3vin[a/b] = off; 12vin[a/b] = off lkg,off( 3vin[a/b]) 3vin[a/b] = off; 12vin[a/b] = off 3vin[a/b]) i il input leakage current il input leakage current il 5 a scl, on[a/b], auxen[a/b], /force_on[a/b] i lkg(off) off-state leakage current gpi_[a0/b0]: i lkg for these two pins 5 a /fault[a/b], /pwrgd[a/b], measured with v lkg(off) /f aul t[a/b], /pwrgd[a/b], measured with v lkg(off) aux /fault[a/b], /pwrgd[a/b], measured with v aux /fault[a/b], /pwrgd[a/b], measured with v off /int, sda, gpi_[a0/b0] t ov overtemperature shutdown and t j increasing, each slot (6) (6) 140 c reset thresholds, with overcurrent on slot t j decreasing, each slot (6) 130 c overtemperature shutdown and t j increasing, both slots (6) (6) 160 c reset thresholds, all other conditions t j decreasing, both slots (6) 150 c (all outputs will latch off) r ds(aux) output mosfet resistance i ds = 375ma, t j = 125c 400 m vaux[a/b] mosfet v off(vaux) off-state output offset voltage v aux[a/b] off-state output offset voltage v aux[a/b] off-state output offset voltage v = off, t j = 125c 50 mv v aux[a/b] v aux[a/b] v notes: 5. speci? cation for packaged product only. 6. parameters guaranteed by design. not 100% production tested. symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units symbol parameter condition min typ max units sf c scaling factor and/or current limit threshold voltages 12v[a/b] supplies 3.3v[a/b] supplies v 12vout[a/b] and 3vout[a/b] v fast-trip threshold voltages v mic2592b-5btq disabled low-level input voltage on[a/b], auxen[a/b], gpi_[a0/b0], /force_on[a/b] output low voltage i /fault[a/b], /pwrgd[a/b], /int, sda high-level input voltage on[a/b], auxen[a/b], gpi_[a0/b0], /force_on[a/b], a[0-2], scl, sda 12vin[a/b] = off; 3vin[a/b] = off 3vin[a/b] = off; 12vin[a/b] = off input leakage current scl, on[a/b], auxen[a/b], /force_on[a/b] off-state leakage current gpi_[a0/b0]: i /fault[a/b], /pwrgd[a/b], measured with v /int, sda, gpi_[a0/b0] overtemperature shutdown and t reset thresholds, with overcurrent on slot t overtemperature shutdown and t reset thresholds, all other conditions t (all outputs will latch off) output mosfet resistance i vaux[a/b] mosfet off-state output offset voltage v v overcurrent delay v scaling factor and/or v 3.3v[a/b] supplies v 12vout[a/b] and 3vout[a/b] v fast-trip threshold voltages v mic2592b-5btq disabled 12vsense[a/b] input current 0.35 a 3vsense[a/b] input current 0.35 a low-level input voltage output low voltage i high-level input voltage on[a/b], auxen[a/b], gpi_[a0/b0], 40 k 12vin[a/b] input leakage current v 12vin[a/b] = off; 3vin[a/b] = off 3vin[a/b] input leakage current v 3vin[a/b] = off; 12vin[a/b] = off input leakage current off-state leakage current gpi_[a0/b0]: i /fault[a/b], /pwrgd[a/b], measured with v /int, sda, gpi_[a0/b0] overtemperature shutdown and t thresholds, with overcurrent on slot t overtemperature shutdown and t reset thresholds, all other conditions t output mosfet resistance i off-state output offset voltage v mic2592b-5btq disabled 12vsense[a/b] input current 0.35 a 3vsense[a/b] input current 0.35 a = 3ma 40 k = vstby[a/b] = +3.3v, 1 a 12vin[a/b] = off; 3vin[a/b] = off = vstby[a/b] = +3.3v, 1 a 3vin[a/b] = off; 12vin[a/b] = off input leakage current for these two pins 140 c 130 c 160 c 150 c = 125c = 125c 5 50 50 100 150 mic2592b-5btq disabled 12vsense[a/b] input current 0.35 a 3vsense[a/b] input current 0.35 a = 3ma 40 k = vstby[a/b] = +3.3v, 1 a 12vin[a/b] = off; 3vin[a/b] = off = vstby[a/b] = +3.3v, 1 a 3vin[a/b] = off; 12vin[a/b] = off input leakage current for these two pins 140 c 130 c 160 c 150 c = 125c = 125c mic2592b-5btq disabled 12vsense[a/b] input current 0.35 a 3vsense[a/b] input current 0.35 a 40 k = vstby[a/b] = +3.3v, 1 a = vstby[a/b] = +3.3v, 1 a 140 c 130 c 160 c 150 c mv mv mv mv 12vsense[a/b] input current 0.35 a 3vsense[a/b] input current 0.35 a v v v 40 k = vstby[a/b] = +3.3v, 1 a = vstby[a/b] = +3.3v, 1 a a a 140 c 130 c 160 c 150 c m mv MIC2592B-2BTQ mic2592b-3btq mic2592b-5btq disabled
march 2005 9 m9999-033105 mic2592b micrel electrical characteristics (continued) (7) symbol parameter condition min typ max units i aux(thresh) auxiliary output current limit current which must be drawn from 0.84 a threshold (figure 4) v aux(thresh) threshold (figure 4) v aux(thresh) aux threshold (figure 4) v aux threshold (figure 4) v to register as a fault i sc(tran) maximum transient short circuit v aux maximum transient short circuit v aux maximum transient short circuit v enabled, then grounded current i v r ma x stby[a /b ] ds(aux) ? a i lim(aux) regulated current after transient from end of i sc(tran) to c filter time-out 0.375 0.7 1.35 a output discharge resistance r dis(12v) 12vout[a/b] 12v out[a/b] = 6.0v 1600 r dis(3v) 3vout[a/b] 3v dis(12v) 3vout[a/b] 3v dis(12v) out[a/b] = 1.65v 150 r dis(vaux) 3vaux[a/b] 3v aux[a/b] 3vaux[a/b] 3v aux[a/b] 3vaux[a/b] 3v = 1.65v 430 t off(12v) 12v current limit response time MIC2592B-2BTQ 1 2.0 s (figure 2) c off(12v) (figure 2) c off(12v) gate = 25pf v in Cv sense = 140mv t off(3v) 3.3v current limit response time MIC2592B-2BTQ 1 2.0 s (figure 3) c off(3v) (figure 3) c off(3v) gate = 25pf v in Cv sense = 140mv (8) t sc(tran) vaux[a/b] current limit response v aux[a/b] vaux[a/b] current limit response v aux[a/b] vaux[a/b] current limit response v = 0v, v stbya = v stbya = v stbya stbyb = +3.3v 2.5 5 s time (figure 5) sc(tran) t ime (figure 5) sc(tran) t prop(12vfault) delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault output c prop(12vfault) limit to /f aul t output c prop(12vfault) filter = 0 v in Cv sense = 140mv (8) t prop(3vfault) delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault[a/b] output c prop(3vfault) limit to /f aul t[a/b] output c prop(3vfault) filter = 0 v in Cv sense = 140mv (8) t prop(vauxfault) delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault[a/b] output prop(vauxfault) limit to /f aul t[a/b] output prop(vauxfault) c filter = 0 v aux v aux v output grounded (8) t w on[a/b], auxen[a/b] pulse width note 8 100 ns t por mic2592b power-on reset time note 8 250 s after vstby[a/b] becomes valid smbus timing t 1 scl (clock) period figure 1 2.5 s t 2 data in setup time to scl high figure 1 100 ns t 3 data out stable after scl low figure 1 300 ns t 4 data low setup time to scl low start condition, figure 1 100 ns t 5 data high hold time after scl high stop condition, figure 1 100 ns notes: 7. speci? cation for packaged product only. 8. parameters guaranteed by design. not 100% production tested. symbol parameter condition min typ max units auxiliary output current limit current which must be drawn from 0.84 a threshold (figure 4) v maximum transient short circuit v current regulated current after transient from end of i output discharge resistance 12vout[a/b] 12v 3vout[a/b] 3v 3vaux[a/b] 3v 12v current limit response time MIC2592B-2BTQ 1 (figure 2) c v 3.3v current limit response time MIC2592B-2BTQ 1 (figure 3) c v vaux[a/b] current limit response v time (figure 5) delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault output c v delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault[a/b] output c v delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault[a/b] output c v on[a/b], auxen[a/b] pulse width after vstby[a/b] becomes valid symbol parameter condition min typ max units auxiliary output current limit current which must be drawn from 0.84 a threshold (figure 4) v maximum transient short circuit v current regulated current after transient from end of i 12vout[a/b] 12v 3vout[a/b] 3v 3vaux[a/b] 3v 12v current limit response time MIC2592B-2BTQ 1 (figure 2) c v 3.3v current limit response time MIC2592B-2BTQ 1 (figure 3) c v vaux[a/b] current limit response v delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault output c v delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault[a/b] output c v delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s limit to /fault[a/b] output c v symbol parameter condition min typ max units auxiliary output current limit current which must be drawn from 0.84 a time-out 0.375 0.7 1.35 a = 6.0v 1600 = 1.65v 150 = 1.65v 430 12v current limit response time MIC2592B-2BTQ 1 3.3v current limit response time MIC2592B-2BTQ 1 = +3.3v 2.5 delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s note 8 250 s time-out 0.375 0.7 1.35 a = 6.0v 1600 = 1.65v 150 = 1.65v 430 12v current limit response time MIC2592B-2BTQ 1 3.3v current limit response time MIC2592B-2BTQ 1 = +3.3v 2.5 delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s 250 s time-out 0.375 0.7 1.35 a = 6.0v 1600 = 1.65v 150 = 1.65v 430 delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s 250 s symbol parameter condition min typ max units auxiliary output current limit current which must be drawn from 0.84 a time-out 0.375 0.7 1.35 a = 6.0v 1600 = 1.65v 150 = 1.65v 430 s s s delay from 12v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from 3v[a/b] overcurrent MIC2592B-2BTQ 1 s delay from vaux[a/b] overcurrent MIC2592B-2BTQ 1 s 250 s symbol parameter condition min typ max units auxiliary output current limit current which must be drawn from 0.84 a symbol parameter condition min typ max units auxiliary output current limit current which must be drawn from 0.84 a scl (clock) period figure 1 data in setup time to scl high figure 1 data out stable after scl low figure 1 data low setup time to scl low start condition, figure 1 data high hold time after scl high stop condition, figure 1 scl (clock) period figure 1 data in setup time to scl high figure 1 data out stable after scl low figure 1 data low setup time to scl low start condition, figure 1 data high hold time after scl high stop condition, figure 1 s ns ns ns ns s ns ns ns ns s ns ns ns ns
mic2592b micrel march 2005 10 m9999-033105 timing diagrams t 1 t 4 scl sda data in sda data out t 2 t 5 t 3 figure 1. smbus timing 6v 12vgate v thfast v thilimit t off(12v) v in C v sense t 0v figure 2. 12v current limit response timing 1v 3vgate v thfast v thilimit t off(3v) v in C v sense 0v t figure 3. 3v current limit response timing i out(aux) i out(aux) i lim(aux) must trip may not trip i aux(thresh) i 0 t figure 4. vaux current limit threshold i out(aux) t sc(tran) i lim(aux) i sc(tran) i o t figure 5. vaux current limit response timing
march 2005 11 m9999-033105 mic2592b micrel typical characteristics 1.20 1.21 1.22 1.23 1.24 1.25 1.26 1.27 1.28 1.29 1.30 0 1 1.20 0 1 1.20 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 cfilter threshold (v) temperature (c) cfilter threshold vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 i filter (a) temperature (c) cfilter charging current vs. temperature 0 0.3 0.4 0.5 0.6 0.7 0.8 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 i lim(aux) (a) temperature (c) auxiliary regulated current vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 supply current (ma) temperature (c) supply current vs. temperature 12v stby 3v 0 1 2 3 4 5 6 7 8 9 10 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 uvlo threshold (v) temperature (c) uvlo threshold vs. temperature 12v stby 3v 0 2 4 6 8 10 12 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 undervoltage threshold (v) temperature (c) power-good undervoltage threshold vs. temperature 12v stby 3v power-good 10 15 20 25 30 35 40 0 1 10 0 1 10 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 gate start-up current (a) temperature (c) gate start-up curent vs. temperature 12v sink 3v charge -0.50 -0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 0 1 -0.50 0 1 -0.50 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 12v gate voltage (v) temperature (c) 12v gate(on) vs. temperature 10.00 10.25 10.50 10.75 11.00 11.25 11.50 11.75 12.00 0 1 10.00 0 1 10.00 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 3v gate voltage (v) temperature (c) 3v gate vs. temperature 0 10 20 30 40 50 60 70 80 90 100 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 gate shutdown current (ma) temperature (c) gate shutdown current vs. temperature 12v pullup 3v sink 45 46 47 48 49 50 51 52 53 54 55 0 1 45 0 1 45 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 current limit (mv) temperature (c) current limit (slow threshold) vs. temperature 12 v 3v 80 85 90 95 100 105 110 115 120 0 1 80 0 1 80 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 fast threshold (mv) temperature (c) current limit (fast threshold) vs. temperature MIC2592B-2BTQ 12 v 3v
mic2592b micrel march 2005 12 m9999-033105 typical characteristics (cont.) 0 100 200 300 400 500 600 700 800 900 1000 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 discharge resistance (?) temperature (c) discharge resistance vs. temperature vaux 3vout 12vout 4.4 4.6 4.8 5.0 5.2 5.4 5.6 0 1 4.4 0 1 4.4 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 scaling factor temperature (c) overcurrent delay scaling factor vs. temperature 0 50 100 150 200 250 300 350 400 0 1 0 0 1 0 0 2 0 3 0 4 0 5 0 6 0 5 0 6 0 5 0 7 0 r ds(on) (?) temperature (c) v aux on-resistance (r ds(on) ) vs. temperature test circuit m2 si4435bdy ona cfiltera gnd 3vina 3vsensea 3vgatea vauxa r1 10k r 3vsensea 0.010 r5 15 c 3vgate 22nf m1 si4410dy 0.1f 0.1f c miller 22nf +3.3v outa +3.3v c filter 0.047f (additional pins omitted for clarity - slot a shown only) auxena vstbya /faulta r2 10k signals under software control r3 10k 12vina 12vsensea 12vgatea r6 15 c in2 220f +12v r 12vsensea 0.025 c gs 10nf 0.1f c load2 100f c load1 100f +12v outa +3.3auxa 12vouta 3vouta mic2592b /pwrgda vstby r4 10k c in1 220f c load3 1f mic2592b test circuit
march 2005 13 m9999-033105 mic2592b micrel time (5ms/div.) 12v out (5v/div.) /fault (5v/div.) i out(12v) (1a/div.) cfilter (1v/div.) 12v overcurrent fault response r load = 3.3 slot a time (5ms/div.) i auxb (500ma/div.) cfilterb (1v/div.) /faultb (5v/div.) auxiliary overcurrent fault response vauxa (2v/div.) r load = 3.3? overcurrent on slot b functional characteristics time (5ms/div.) 3v out (2v/div.) /fault (5v/div.) i out(3v) (2a/div.) cfilter (1v/div.) 3v overcurrent fault response r load = 0.4 slot a time (5ms/div.) i out(12v) (1a/div.) /faulta (5v/div.) cfiltera (1v/div.) /faultb (1v/div.) overcurrent fault response channel independent r load = 3.3 overcurrent on slot a, 12v supply time (2.5ms/div.) 12v out (5v/div.) /pwrgd (5v/div.) 3v out (2v/div.) v aux (2v/div.) turn-on response slot a time (5ms/div.) 12vgate (5v/div.) 3vgate (5v/div.) on (5v/div.) gate output turn-on response slot a
mic2592b micrel march 2005 14 m9999-033105 time (250ms/div.) /pwrgd (2v/div.) 12v out (2v/div.) 12v ouput discharge response output disabled by on pin c load = 1000f i out = 0a v uv(12v) time (25ms/div.) /pwrgd (2v/div.) 3v out (1v/div.) 3v ouput discharge response output disabled by on pin c load = 1000f i out = 0a v uv(3v) functional characteristics cont. time (500s/div.) 12vin &vstby (5v/div.) /fault (5v/div.) 3vin (1v/div.) 3v undervoltage fault response main(12v and 3.3v) supplies enabled slot a v uvlo(3v) +3vin /fault +12vin vstby time (500s/div.) vstby (2v/div.) 3vin (2v/div.) /fault (5v/div.) 12vin (5v/div.) 12v undervoltage fault response main(12v and 3.3v) supplies enabled slot a v uvlo(12v) +12vin /fault +12vin vstby
march 2005 15 m9999-033105 mic2592b micrel functional block diagram logic circuits vaux pwrgd thermal shutdown on/off vaux charge pump & mosfet vaux overcurrent bandgap reference 3vin[a/b] v ref v ref digital core/serial interface 12vin[a/b] v ref 12v bias power-on reset 250 ? s 3v uvlo 12v uvlo on/off on/off on/off on/off 50mv 50mv 100mv* 100mv* v stby(ref) current mirror overcurrent detection rfilter[a&b] open pin detector v ref i ref v stby(ref) 40k? ? 3 12vgate[a/b] vaux[a/b] 3vgate[a/b] /pwrgd[a/b] /fault[a/b] 3vout[a/b] 12vout[a/b] 3vpwrgd 12vpwrgd /int gnd a0 a1 a2 sda scl gpi_[a0/b0] /force_on[a/b] rfilter[a&b] cfilter[a/b] 3vin[a/b] 3vsense[a/b] 12vin[a/b] 12vsense[a/b] on[a/b] aux[a/b] vstby[a/b] vstby uvlo * mic2592b-3btq fast threshold is 150mv mic2592b-5btq fast threshold is disabled contact factory for availabilty mic2592b block diagram
mic2592b micrel march 2005 16 m9999-033105 mic2592b a2 /int sda scl a0 v stby v stby a1 100k 47 48 37 39 40 41 100k disabling smi when hpi control is used disabling hpi when smi control is used 100k /int /force_onb 100k 100k /force_ona auxena auxenb ona onb mic2592b 9 28 45 42 44 43 figure 6. input pin con? guration for disabling hpi/smi control functional description hot swap insertion when circuit boards are inserted into systems carrying live supply voltages (hot-plugged), high inrush currents often result due to the charging of bulk capacitance that resides across the circuit boards supply pins. this transient inrush current can cause the systems supply voltages to temporarily go out of regulation, causing data loss or system lock-up. in more extreme cases, the transients occurring during a hot- plug event may cause permanent damage to connectors or on-board components. the mic2592b addresses these issues by limiting the in- rush currents to the load (pci express board), and thereby controlling the rate at which the loads circuits turn-on. in addition to this inrush current control, the mic2592b offers input and output voltage supervisory functions and current limiting to provide robust protection for both the system and circuit board. system interface the mic2592b employs two system interfaces: the hard- ware hot-plug interface (hpi) and the system management interface (smi). the hpi includes on[a/b], auxen[a/b], as well as /fault[a/b]; the smi consists of sda, scl, and /int, whose signals conform to the levels and timing of the smbus speci? cation. the mic2592b can be operated exclusively from the smi, or can employ the hpl for power control while continuing to use the smi for access to all but the power control registers. in addition to the basic power control features of the mic2592b accessible by the hpi, the smi also gives the host access to the following information from the part: ? fault conditions occurring on each supply. ? gpi_[a0/b0] pin status when using the system management interface for power control, do not use the hot-plug interface. conversely, when using the hot-plug interface for power control, do not execute power control commands over the system management interface bus (all other register accesses via the smi bus remain permissible while in the hpi control mode). when utilizing the smi exclusively, the hpi input pins (on[a/b], auxen[a/b], and /force_on[a/b]) should be con? gured as shown below in figure 6 (disabling hpi when smi control is used). this con? guration safeguards the power slots in the event that the smbus communication link is disconnected for any reason. additionally, when utilizing the hpi exclusively, the smbus (or smi) will be inactive if the input pins (sda, scl, a0, a1, and a2) are con? gured as shown in figure 6 below (disabling smi when hpi control is used). power stability and power-on reset the mic2592b utilizes vstby[a/b] as the main supply input source. vstby[a/b] is required for proper operation of the mic2592bs smbus and registers and must be applied at all times. to ensure that the mic2592b controller operates properly, the v stby input must be stable and remain above stby input must be stable and remain above stby the undervoltage lockout (uvlo) threshold once applied. suf? cient input bulk capacitance should be used to prevent the supply from "drooping", causing vstby[a/b] to fall below the uvlo threshold. also, decoupling capacitors should be placed at each of the mic2592b inputs in order to ? lter high frequency noise transients. v stby must be the ? rst supply input applied followed by the stby must be the ? rst supply input applied followed by the stby main supply inputs of 12v in and 3v in . a power-on reset (por) cycle is initiated after vstby[a/b] rises above its uvlo threshold and remains valid at that voltage for 250s. all internal registers are cleared after por. if vstby[a/b] is recycled, the mic2592b enters a new power-on-reset cycle. the smbus is ready for access at the end of the por cycle (250s after vstby[a/b] is valid). during t por , all outputs remain off. in most applications, the total por interval will consist of the time required to charge the v stby input (by- stby input (by- stby pass) capacitance to the uvlo threshold plus the internal t por . the following equation is used to approximate the total por interval: t por_total(s) = c stby(f) ? v ulvo(stby) i charge(stby) (a) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t por (s) ? 10 6 where c stby is the v stby is the v stby stby input bulk bypass capacitance and stby input bulk bypass capacitance and stby i charge(stby) is the current supplied by the v stby source stby source stby to charge the capacitance. charge(stby) to charge the capacitance. charge(stby) power-up cycle enabling the gate output when a slot's main supplies are off, the 12vgate pin is held high with an internal pull-up. similarly, the 3vgate pin is internally held low. when the main supplies of the mic2592b are enabled by asserting on[a/b], the 3vgate[a/b] and 12vgate[a/b] pins are each connected to a constant cur- rent supply. these supplies are each nominally 25a. for a slots 3vgate pin, this is a current source; for the 12vgate pin, this is a current sink.
march 2005 17 m9999-033105 mic2592b micrel inrush current and load dominated start-up the expected maximum inrush current can be calculated by using the following equation: inrush i c c 25 a c c gate load gate load gat e ? ? ? ? ? where ? i gate ? is the gate pin current, i gate(3vcharge) or i gate(12vsink) , c load is the load capacitance, and gate(3vcharge) is the load capacitance, and gate(3vcharge) c gate is the total gate capacitance (c gate(12vsink) is the total ga te capacitance (c gate(12vsink) iss of the external mosfet and any external capacitance connected from the gate output pin to the gate reference C gnd or source). for the 3.3v outputs and 12v outputs (if no external 12vgate output capacitors are implemented), the following equation is used to determine the output slew rate. dv dt i c out lim 3v 12v load 3v 12v ? ? ? ? ? ? ? ? consequently, the overcurrent timer delay must be pro- grammed to exceed the time it will take to charge the output load to the input rail voltage level. main outputs (start-up delay and slew-rate control) the 3.3v outputs act as source followers. in this mode of operation,v source = [v gate C v th(on) ] until the associated output reaches 3.3v. the voltage on the gate of the mosfet th(on) output reaches 3.3v . the voltage on the gate of the mosfet th(on) will then continue to rise until it reaches 12v, which ensures minimum r ds(on) . note that a delay exists between the on command to a slot and the appearance of voltage at the slots ds(on) command to a slot and the appearance of voltage at the slot s ds(on) 3.3v output. this delay is the time required to charge the 3vgate output up to the threshold voltage of the external mosfet (typically about 3v). t c v i 3vdly gate gs(th ) gate(3vcharge ) ? ? ? ? the source (output) side of the external mosfet will reach the drain voltage in a time given by: t t c v i 3v(source_drain) 3vdly load drain lim(3v) ? ? ? ? ? for the 12v outputs, each mosfet is con? gured as a miller integrator (by virtue of c miller , which is connected between the mosfets gate and drain). in this con? guration, the feedback action from drain to gate of the mosfet causes the voltage at the drain of the mosfet to slew in a linear fashion at a rate which satis? es the following equation: dv / dt(12v) i c gate miller ? ? ? ? ? ? ? ? a delay exists between the on command to a slot and the appearance of voltage at the slots 12v output. for a slots 12v output, that delay is given by the time required for the capacitor from the gate of the mosfet to its source (typically ? ve times the value of c miller ) to charge to the threshold voltage of the mosfet (typically about 3v). in this instance, the delay before the output voltage starts ramping can be approximated by: t c v i vdly gate(total) gs(th ) gate 12 ? ? ? ? where c gate(total) is the sum of the c gs of the external mosfet, any external capacitance from the gate output of gate(total) mosfet , any external capacitance from the ga te output o f gate(total) the mic2592b to the source of the mosfet, and c miller (external, if used). table 1 approximates the output slew-rate for various values of c gate when start-up is dominated by gate capacitance (external c gate from gate pin to ground plus c gs of the ex- ternal mosfet for the 3.3v rail; c miller for the 12v rail). | i gate | = 25a c gate or c miller dv/dt (load) 0.01f* 2.5v/ms 0.022f* 1.136v/ms 0.047f 0.532 v/ms 0.1f 0.250v/ms * values in this range will be affected by the internal parasitic capaci- tances of the mosfets used, and should be veri? ed experimentally. table 1. 3.3v and 12v output slew-rate selection for gate capacitance dominated start-up power-down cycle when one or more pci slots are disabled via the mic2592b output control pins, on[a/b] or auxen[a/b], the output volt- age for each supply will discharge as a function of the rc time constant produced by the controllers internal resistance (r dis ) connected to the output and the load capacitance (c load ). the typical value of r dis for each supply is listed in the electrical characteristics table. the charts below in figure 7 display curves of the fall time (90% - 10%) as a function of the output load capacitance for both the 3v and 12v main outputs. 0 200 400 600 800 1000 1200 0 5 0 0 5 0 0 0 5 0 0 5 100 150 200 250 load capacitance (f) fall time (ms) 3v output discharge as a function of load capacitance 0 200 400 600 800 1000 1200 0 0 0 0 500 1000 1500 2000 2500 load capacitance (f) fall time (ms) 12v output discharge as a function of load capacitance figure 7. 3v and 12v output discharge vs. load capacitance standby mode standby mode is entered when one or more of the main supply inputs (12vin and/or 3vin) is below its respective uvlo threshold or off. the mic2592b also supplies 3.3v auxiliary outputs (vaux[a/b]), satisfying pci express speci? cations. these outputs are fed via the vstby[a/b] input pins and controlled by the auxen[a/b] input pins or via their respective bits in the control registers. these 0.01f* 2.5v/ms 0.022f* 1.136v/ms 0.047f 0.532 v/ms 0.1f 0.250v/ms dv/dt (load) 0.01f* 2.5v/ms 0.022f* 1.136v/ms 0.047f 0.532 v/ms 0.1f 0.250v/ms
mic2592b micrel march 2005 18 m9999-033105 v stby 4.99 k /pwrgd[a/b] auxen[a/b] (1) on[a/b] (1) force_on[a/b] (1) (1) external pin (2) cntrl[a/b] register bit d[0] (3) internal flag (4) cntrl[a/b] register bit d[1] (5) cntrl[a/b] register bit d[2] main[a/b] (4) vaux[a/b] (2) 3vaux_uv[a/b] (3) force_en[a/b] (5) 12vout_uv[a/b] (3) 3vout_uv[a/b] (3) figure 8. /pwrgd[a/b] logic diagram outputs are independent of the main outputs (12vin[a/b] and 3vin[a/b]). should the main supply inputs move below their respective uvlo thresholds, vaux[a/b] will still function as long as vstby[a/b] is present. prior to standby mode, ona and onb (or the control registers' maina and mainb bits) inputs should be deasserted or the mic2592b will assert /fault[a/b] and /int (if inter- rupts are enabled) output signals, if an undervoltage condi- tion on the main supply inputs is detected. circuit breaker function the mic2592b provides an electronic circuit breaker func- tion that protects against excessive loads, such as short circuits, at each supply. when the current from one or more of a slots main outputs exceeds the current limit threshold (i lim = 50mv/r sense ) for a duration greater than t flt , the flt , the flt circuit breaker is tripped and both main supplies (all outputs except vaux[a/b]) are shut off. should the load current cause a main outputs v sense to exceed v thfast , the outputs are thfast , the outputs are thfast immediately shut off with no delay. undervoltage conditions on the main supply inputs also trip the circuit breaker, but only when the main outputs are enabled (to signal a supply input brown-out condition). the vaux[a/b] outputs have a different circuit-breaker func- tion. the vaux[a/b] circuit breakers do not incorporate a fast-trip detector, instead they regulate the output current into a fault to avoid exceeding their operating current limit. the circuit breaker will trip due to an overcurrent on vaux[a/b] when the fault timer expires. this use of the t flt timer pre- flt timer pre- flt vents the circuit breaker from tripping prematurely due to brief current transients. following a fault condition, the outputs can be turned on again via the on inputs (if the fault occurred on one of the main outputs), via the auxen inputs (if the fault occurred on the aux outputs), or by cycling both on and auxen (if faults occurred on both the main and aux outputs). a fault condition can alternatively be cleared under smi control of the enable bits in the cntrl[a/b] registers (see register bits d[1:0]). when the circuit breaker trips, /fault[a/b] will be asserted if the outputs were enabled through the hot-plug interface inputs. at the same time, /int will be asserted (un- less interrupts are masked). note that /int is deasserted by writing a logic 1 back into the respective fault bit position(s) in the stat[a/b] register or the common status register. the response time (t flt ) of the mic2592bs primary overcur- rent detector is set by external capacitors at the cfilter[a/b] pins to gnd. for slot a, cfilter[a] is located at pin 2; for slot b, cfilter[b] is located at pin 35. for a given response time, the value for c filter[a/b] is given by: c f t m s i a v v 10 filter[a /b ] flt a b filter filter 3 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? where t flt[a/b] is the desired response time and quantities i filter and v flt[a/b] and v flt[a/b] filter are speci? ed in the mic2592bs electri- cal characteristics table. for applications that require a more accurate response time for a given c filter[a/b] tolerance, the mic2592b employs a patent-pending technique that improves re- filter[a/b] e m p l o y s a p a t e n t - p e n d i n g t e c h n i q u e t h a t i m p r o v e s r e - filter[a/b] sponse time accuracy by more than a factor of two. a 110k, 1% resistor connected from the mic2592bs rfilter[a&b] pin (pin 20) to gnd can be used. in this case, the value for c filter[a/b] for a desired response time (t flt ) is given by: c f t m s r k sf filter[a /b ] flt filter[a &b ] ? ? ? ? ? ? ? ? ? ? where t flt is the desired response time, r filter[a&b] is 110k ? , and sf is the cfilter[a/b] response time filter[a&b] , and sf is the cfil ter[a/b] response time filter[a&b] scaling factor in the electrical characteristics table.
march 2005 19 m9999-033105 mic2592b micrel thermal shutdown the internal vaux[a/b] mosfets are protected against damage not only by current limiting, but by dual-mode overtemperature protection as well. each slot controller on the mic2592b is thermally isolated from the other. should an overcurrent condition raise the junction temperature of one slots controller and pass elements to 140c, all of the outputs for that slot (including vaux) will be shut off and the slots /fault output will be asserted. the other slots operating condition will remain unaffected. however, should the mic2592bs die temperature exceed 160c, both slots (all outputs, including vauxa and vauxb) will be shut off, whether or not a current limit condition exists. a 160c over- temperature condition additionally sets the overtemperature bit (ot_int) in the common status register. /pwrgd[a/b] outputs the mic2592b has two /pwrgd outputs, one for each slot. these are open-drain, active-low outputs that require an external pull-up resistor to v stby . each output is asserted stby . each output is asserted stby when a slot has been enabled and has successfully begun delivering power to its respective +12v, +3.3v, and vaux outputs. an equivalent logic diagram for /pwrgd[a/b] is shown in figure 8. /force_on[a/b] inputs these level-sensitive, active-low inputs are provided to facilitate designing systems using the mic2592b. asserting /force_on[a/b] will turn on all three of the respective slots outputs (+12v, +3.3v, and vaux), while speci? cally defeating all protections for those outputs. this explicitly includes all overcurrent and short circuit protections, and on-chip thermal protection for the vaux supplies. additionally, asserting a slots /force_on[a/b] input will disable all of its input and output uvlo protections, with the sole exception of that as- serting either or both of the /force_on[a/b] inputs will not disable the vstby[a/b] input uvlo. asserting /force_on[a/b] will cause the respective slots /pwrgd[a/b] and /fault[a/b] outputs to enter their open- drain state. additionally, there are two smbus accessible register bits (see cntrl[a/b] register bit d[2]), which can be set to disable the corresponding slots /force_on[a/b] pins. this allows system software to prevent these hardware overrides from being inadvertently activated during normal use. if not used, each pin should be connected to v stby using stby using stby an external pull-up resistor. see figure 6 for details. general purpose input (gpi) pins two pins on the mic2592b are available for use as gpi pins. the logic state of each of these pins can be determined by polling bits [4:5] of common status register. both of these inputs are compliant to 3.3v. if unused, connect each gpi_[a0/b0] pin to gnd. hot-plug interface (hpi) once the input supplies are above their respective uvlo thresholds, the hot-plug interface can be utilized for power control by enabling the control input pins (auxen[a/b] and on[a/b]) for each slot. in order for the mic2592b to switch on the vaux supply for either slot, the auxen[a/b] control must be enabled after the power-on-reset delay, t por (typi- cally, 250 s), has elapsed. the timing response diagram of figure 9 illustrates a hot-plug interface operation where an overcurrent fault is detected by the mic2592b controller after initiating a power-up sequence. the main (+12v & +3.3v) and vaux[a/b] supply rails, /fault, /pwrgd and /int output responses for both aux and main are shown in the ? gure. system management interface (smi) the mic2592bs system management interface uses the read_byte and write_byte subset of the smbus protocols to communicate with its host via the system management interface bus. the /int output signals the controlling proces- sor that one or more events need attention, if an interrupt- driven architecture is used. note that the mic2592b does not participate in the smbus alert response address (ara) portion of the smbus protocol. fault reporting and interrupt generation smi-only control applications in applications where the mic2592b is controlled only by the smi, on[a/b] and auxen[a/b] are connected to gnd and the /force_on[a/b] pins are connected to v stby as stby as stby shown in figure 6. in this case, the mic2592bs /fault[a/b] outputs and stat[a/b] register bit d[7] (fault[a/b]) are not activated as fault status is determined by polling stat[a/b] register bits d[4], d[2], d[0] and cs (common status) register bits d[2:1]. individual fault bits in stat[a/b] and cs registers are asserted after power-on-reset when: ? either or both cntrl[a/b] register bits d[1:0] are asserted, and ? 12vin[a/b], 3vin[a/b], or vstby[a/b] input volt- age is lower than its respective ulvo threshold, or ? the fast oc circuit breaker[a/b] has tripped, or ? the slow oc circuit breaker[a/b] has tripped and its ? lter timeout has expired, or ? the slow oc circuit breaker[a/b] has tripped and slot[a/b] die temperature > 140c, or ? the mic2592bs global die temperature > 160c to clear any one or all stat[a/b] register bits d[4], d[2], d[0] and/or cs register bits d[2], d[1] once asserted, a software subroutine can perform an echo reset where a logical 1 is written back to those register bit locations that have indicated a fault. this method of echo reset allows data to be retained in the stat[a/b] and/or cs registers until such time as the system is prepared to operate on that data. the mic2592b can operate in interrupt mode or polled mode. for interrupt-mode operation, the open-drain, active-low /int output signal is activated after power-on-reset if the intmsk bit (cs register bit d[3]) has been reset to logical 0. once activated, the /int output is asserted by any one of the fault conditions listed above and deasserted when one or all stat[a/b] register bits d[4], d[2], d[0] and/or cs register bits d[2], d[1] are reset upon the execution of an smbus echo reset write_byte cycle. for polled-mode operation, the intmsk bit should be set to logical 1, thereby inhibiting /int output pin operation. for those smi-control applications where the /force_on[a/b]
mic2592b micrel march 2005 20 m9999-033105 s 1 0 0 0 a2 a1 a0 0 a 0 0 0 0 0 0 x x a d4 d5 d6 d3 d2 d1 d0 d7 a p mic2592b device address data clk command byte to mic2592b data byte to mic2592b start stop r/w = write acknowledge acknowledge acknowledge master to device transfer, i.e., data driven by master. device to master transfer, i.e., data driven by device. figure 10. write_byte protocol s 1 0 0 0 a2 a1 a0 a2 a1 a0 0 a 0 0 0 0 0 0 x x a s 1 0 1 0 0 d4 d5 d6 d3 d2 d1 d0 a d7 /a p mic2592b device address data clk command byte to mic2592b mic2592b device address data read from mic2592b start start stop r/w = write r/w = read acknowledge acknowledge acknowledge not acknowledge master to device transfer, i.e., data driven by master. device to master transfer, i.e., data driven by device. figure 11. read_byte protocol s 1 0 0 0 a2 a1 a0 1 a d4 d5 d6 d3 d2 d1 d0 d7 /a p mic2592b device address data clk byte read from mic2592b start stop r/w = read acknowledge not acknowledge master to device transfer, i.e., data driven by master. device to master transfer, i.e., data driven by device. figure 12. receive_byte protocol /int* /fault_[a/b] i 3vout[a/b] 3vout[a/b] i aux_out[a/b] vaux_out[a/b] auxen[a/b] 0 0 v ih v ih v il v ih i lim(3v) i steady-state on[a/b] 0 0 0 0 0 0 0 v ih v il +3.3v t por vstby uvlo t flt t flt i lim(aux) i steady-state 0 0 * * * /int de-asserted by software 12vout[a/b] /pwrgd_[a/b] figure 9. hot-plug interface operation
march 2005 21 m9999-033105 mic2592b micrel mic2592b register set and programmers model target register command byte value power-on default label description read write cntrla control register slot a 02 h 02 h 00 h cntrlb control register slot b 03 h 03 h 00 h stata slot a status 04 h 04 h 00 h statb slot b status 05 h 05 h 00 h cs common status register 06 h 06 h xxxx 0000 b reserved reserved / do not use 07h - ff h 07h - ff h unde? ned table 2. mic2592b register addresses label description read write cntrla control register slot a 02 cntrlb control register slot b 03 stata slot a status 04 statb slot b status 05 cs common status register 06 reserved reserved / do not use 07h - ff target register command byte value power-on default label description read write cntrla control register slot a 02 cntrlb control register slot b 03 stata slot a status 04 statb slot b status 05 cs common status register 06 reserved reserved / do not use 07h - ff label description read write 02 03 04 05 06 07h - ff target register command byte value power-on default 00 00 00 00 xxxx 0000 unde? ned h h default label description read write cntrla control register slot a 02 cntrlb control register slot b 03 stata slot a status 04 statb slot b status 05 cs common status register 06 reserved reserved / do not use 07h - ff inputs mic2592b device address a2 a1 a0 binary hex 0 0 0 1000 000x* b 80 h 0 0 1 1000 001x b 82 h 0 1 0 1000 010x b 84 h 0 1 1 1000 011x b 86 h 1 0 0 1000 100x b 88 h 1 0 1 1000 101x b 8a h 1 1 0 1000 110x b 8c h 1 1 1 1000 111x b 8e h * where x = "1" for read and "0" for write table 3. mic2592b smbus addressing inputs mic2592b device address a2 a1 a0 binary hex 0 0 0 1000 000x* 0 0 1 1000 001x 0 1 0 1000 010x 0 1 1 1000 011x 1 0 0 1000 100x 1 0 1 1000 101x 1 1 0 1000 110x 1 1 1 1000 111x a2 a1 a0 binary hex 0 0 0 1000 000x* 0 0 1 1000 001x 0 1 0 1000 010x 0 1 1 1000 011x 1 0 0 1000 100x 1 0 1 1000 101x 1 1 0 1000 110x 1 1 1 1000 111x a2 a1 a0 binary hex 0 0 0 1000 000x* 0 0 1 1000 001x 0 1 0 1000 010x 0 1 1 1000 011x 1 0 0 1000 100x 1 0 1 1000 101x 1 1 0 1000 110x 1 1 1 1000 111x a2 a1 a0 binary hex 80 82 84 86 88 8a 8c 8e inputs are needed for diagnostic purposes, the /force_on[a/b] inputs must be enabled; that is, cntrl[a/b] register bit d[2] should read logical 0. once /force_on[a/b] inputs are asserted, all output voltages are present with all circuit protection features disabled, including overtemperature protection on vaux[a/b] outputs. to inhibit /force_on[a/b] operation, a logical 1 shall be written to the cntrl[a/b] register bit d[2] location(s). hpi-only control applications in applications where the mic2592b is controlled only by the hpi, smbus signals scl, sda, and /int signals are con- nected to v stby as shown in figure 6. in this con? guration, stby as shown in figure 6. in this con? guration, stby the mic2592bs /fault[a/b] outputs are activated after power-on-reset and become asserted when: either or both external on[a/b] and auxen[a/b] input signals are asserted, and ? 12vin[a/b], 3vin[a/b], or vstby[a/b] input volt- age is lower than its respective ulvo threshold, or ? the fast oc circuit breaker[a/b] has tripped, or ? the slow oc circuit breaker[a/b] has tripped and its ? lter timeout[a/b] has expired, or ? the slow oc circuit breaker[a/b] has tripped and slot[a/b] die temperature > 140c, or ? the mic2592bs global die temperature > 160c in order to clear /fault[a/b] outputs once asserted, either or both on[a/b] and auxen[a/b] input signals must be deasserted. please see /fault[a/b] pin description for ad- ditional information. if the /force_on[a/b] inputs are used for diagnostic pur- poses, both /fault[a/b] and /pwrgd[a/b] outputs are deasserted once /force_on[a/b] inputs are asserted. serial port operation the mic2592b uses standard smbus write_byte and read_byte operations for communication with its host. the smbus write_byte operation involves sending the devices target address, with the r/w bit (lsb) set to the low (write) state, followed by a command byte and a data byte. the smbus read_byte operation is similar, but is a composite write and read operation: the host ? rst sends the devices target address followed by the command byte, as in a write operation. a new start bit must then be sent to the mic2592b, followed by a repeat of the device address with the r/w bit set to the high (read) state. the data to be read from the part may then be clocked out. there is one exception to this rule: if the location latched in the pointer register from the last write operation is known to be correct (i.e., points to the desired register within the mic2592b), then the receive_byte procedure may be used. to perform a receive_byte operation, the host sends an address byte to select the target mic2592b, with the r/w bit set to the high (read) state, and then retrieves the data byte. figures 10 through 12 show the formats for these data read and data write procedures. the command register is eight bits (one byte) wide. this byte carries the address of the mic2592bs register to be operated upon. the command byte values corresponding to the various mic2592b register addresses are shown in table 2. command byte values other than 0000 0xxx b = 00 h C 07 h are reserved and should not be used. mic2592b smbus address con? guration the mic2592b responds to its own unique smbus address, which is assigned using a2, a1, and a0. these represent the 3 lsbs of its 7-bit address, as shown in table 3. these address bits are assigned only during power up of the vstby[a/b] supply input. these address bits allow up to eight mic2592b devices in a single system. these pins are either grounded or left unconnected to specify a logical 0 or logical 1, respectively. a pin designated as a logical 1 may also be pulled up to v stby . stby . stby
mic2592b micrel march 2005 22 m9999-033105 detailed register descriptions control register, slot a (cntrla) 8-bits, read/write control register, slot a (cntrla) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa enable bit(s) function operation auxapg aux output power-good status, slot a 1 = power-is-good (vauxa output is above its uvlo threshold) mainapg main output power-good status, slot a 1 = power-is-good (maina outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero /force_a allows or inhibits the operation of the /force_ona 0 = /force_ona is enabled enable input pin 1 = /force_ona is disabled maina main enable control, slot a 0 = off, 1 = on vauxa vaux enable control, slot a 0 = off, 1 = on power-up default value: 0000 0000b = 00h read command_byte value (r/w): 0000 0010b = 02h the power-up default value is 00h. slot is disabled upon power-up, i.e., all supply outputs are of f. notes: 1. the state of the /pwrgda pin is the logical and of the values of the auxapg and the mainapg bits, except when /force_ona is asserted. if /force_ona is asserted (the pin is pulled low), and /force_aenable is set to a logic zero, the /pwrgda pin will be unconditionally forced to its open-drain (power not good) state. bit(s) function operation auxapg aux output power-good status, slot a 1 = power-is-good (vauxa output is above its uvlo threshold) mainapg main output power-good status, slot a 1 = power-is-good (maina outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero /force_a allows or inhibits the operation of the /force_ona 0 = /force_ona is enabled enable input pin 1 = /force_ona is disabled maina main enable control, slot a 0 = off, 1 = on vauxa vaux enable control, slot a 0 = off, 1 = on bit(s) function operation auxapg aux output power-good status, slot a 1 = power-is-good (vauxa output is above its uvlo threshold) mainapg main output power-good status, slot a 1 = power-is-good (maina outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero /force_a allows or inhibits the operation of the /force_ona 0 = /force_ona is enabled enable input pin 1 = /force_ona is disabled maina main enable control, slot a 0 = off, 1 = on vauxa vaux enable control, slot a 0 = off, 1 = on d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxapg mainapg reserved reserved reserved /force_a maina vauxa
march 2005 23 m9999-033105 mic2592b micrel control register, slot b (cntrlb) 8-bits, read/write control register, slot b (cntrlb) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb enable bit(s) function operation auxbpg aux output power-good status, slot b 1 = power-is-good (vauxb output is above its uvlo threshold) mainbpg main output power-good status, slot b 1 = power-is-good (mainb outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero /force_b allows or inhibits the operation of the /force_onb 0 = /force_onb is enabled enable input pin 1 = /force_onb is disabled mainb main enable control, slot b 0 = off, 1 = on vauxb vaux enable control, slot b 0 = off, 1 = on power-up default value: 0000 0000b = 00h command_byte value (r/w): 0000 0011b = 03h the power-up default value is 00h. slot is disabled upon power-up, i.e., all supply outputs are of f. notes: 1. the state of the /pwrgdb pin is the logical and of the values of the auxbpg and the mainbpg bits, except when /force_onb is asserted. if /force_onb is asserted (the pin is pulled low), and /force_benable is set to a logic zero, the /pwrgdb pin will be unconditionally forced to its open-drain (power not good) state. bit(s) function operation auxbpg aux output power-good status, slot b 1 = power-is-good (vauxb output is above its uvlo threshold) mainbpg main output power-good status, slot b 1 = power-is-good (mainb outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero /force_b allows or inhibits the operation of the /force_onb 0 = /force_onb is enabled enable input pin 1 = /force_onb is disabled mainb main enable control, slot b 0 = off, 1 = on vauxb vaux enable control, slot b 0 = off, 1 = on bit(s) function operation auxbpg aux output power-good status, slot b 1 = power-is-good (vauxb output is above its uvlo threshold) mainbpg main output power-good status, slot b 1 = power-is-good (mainb outputs are above their uvlo thresholds) d[5] reserved always read as zero d[4] reserved always read as zero d[3] reserved always read as zero /force_b allows or inhibits the operation of the /force_onb 0 = /force_onb is enabled enable input pin 1 = /force_onb is disabled mainb main enable control, slot b 0 = off, 1 = on vauxb vaux enable control, slot b 0 = off, 1 = on d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb enable d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read only read only read-only read/write read/write read/write auxbpg mainbpg reserved reserved reserved /force_b mainb vauxb
mic2592b micrel march 2005 24 m9999-033105 status register slot a (stata) 8-bits, read-only status register, slot a (stata) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf bit(s) function operation faulta fault status - slot a 1 = fault pin asserted (/faulta pin is low) 0 = fault pin deasserted (/faulta pin is high) see notes 1, 2, and 3. maina main enable status - slot a represents the actual state (on/off) of the two main power outputs for slot a (+12v and +3.3v) 1 = main power on 0 = main power off vauxa vaux enable status - slot a represents the actual state (on/off) of the auxiliary power output for slot a 1 = aux power on 0 = aux power off vauxaf overcurrent fault: vauxa supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vaf overcurrent fault: +12v supply 1 = fault 0 = no fault d[1] reserved always read as zero 3vaf overcurrent fault: 3.3v supply 1 = fault 0 = no fault power-up default value: 0000 0000b = 00h command_byte value (r/w): 0000 0100b = 04h the power-up default value is 00h. both slots are disabled upon power-up, i.e., all supply outputs are off. in response to an overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /int. the status of the /faulta pin is not affected by reading the status register or by clearing active status bits. notes: 1. if faulta has been set by an overcurrent condition on one or more of the main outputs, the ona input must go low to reset faulta. if faulta has been set by a vauxa overcurrent event, the auxena input must go low to reset faulta. if an overcurrent has occurred on both a main output and the vaux output of slot a, both ona and auxena of the slot must go low to reset faulta. 2. neither the faulta bits nor the /faulta pins are active when the mic2592b power paths are controlled by the system management interface. when using smi power path control, auxena and ona pins for that slot must be tied to gnd. bit(s) function operation faulta fault status - slot a 1 = fault pin asserted (/faulta pin is low) 0 = fault pin deasserted (/faulta pin is high) see notes 1, 2, and 3. maina main enable status - slot a represents the actual state (on/off) of the two main power outputs for slot a (+12v and +3.3v) 1 = main power on 0 = main power off vauxa vaux enable status - slot a represents the actual state (on/off) of the auxiliary power output for slot a 1 = aux power on 0 = aux power off vauxaf overcurrent fault: vauxa supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vaf overcurrent fault: +12v supply 1 = fault 0 = no fault d[1] reserved always read as zero 3vaf overcurrent fault: 3.3v supply 1 = fault 0 = no fault bit(s) function operation faulta fault status - slot a 1 = fault pin asserted (/faulta pin is low) 0 = fault pin deasserted (/faulta pin is high) see notes 1, 2, and 3. maina main enable status - slot a represents the actual state (on/off) of the (+12v and +3.3v) 1 = main power on 0 = main power off vauxa vaux enable status - slot a represents the actual state (on/off) of the 1 = aux power on 0 = aux power off vauxaf overcurrent fault: vauxa supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vaf overcurrent fault: +12v supply 1 = fault 0 = no fault d[1] reserved always read as zero 3vaf overcurrent fault: 3.3v supply 1 = fault 0 = no fault d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faulta maina vauxa vauxaf reserved 12vaf reserved 3vaf faulta fault status - slot a 1 = fault pin asserted (/faulta pin is low) 0 = fault pin deasserted (/faulta pin is high) see notes 1, 2, and 3. maina main enable status - slot a represents the actual state (on/off) of the two main power outputs for slot a (+12v and +3.3v) 1 = main power on 0 = main power off vauxa vaux enable status - slot a represents the actual state (on/off) of the auxiliary power output for slot a 1 = aux power on 0 = aux power off vauxaf overcurrent fault: vauxa supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vaf overcurrent fault: +12v supply 1 = fault 0 = no fault maina main enable status - slot a represents the actual state (on/off) of the vauxa vaux enable status - slot a represents the actual state (on/off) of the
march 2005 25 m9999-033105 mic2592b micrel status register slot b (statb) 8-bits, read-only status register, slot b (statb) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf bit(s) function operation faultb fault pin status - slot b 1 = fault pin asserted (/faultb pin is low) 0 = fault pin deasserted (/faultb pin is high) see notes 1, 2, and 3. mainb main enable status - slot b represents the actual state (on/off) of the four main power outputs for slot b (+12v and +3.3v) 1 = main power on 0 = main power off vauxb vaux enable status - slot b represents the actual state (on/off) of the auxiliary power output for slot b 1 = aux power on 0 = aux power off vauxbf overcurrent fault: vauxb supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vbf overcurrent fault: +12v supply 1 = fault 0 = no fault d[1] reserved always read as zero 3vbf overcurrent fault: 3.3v supply 1 = fault 0 = no fault power-up default value: 0000 0000b = 00h command_byte value (r/w): 0000 0101b = 05h the power-up default value is 00h. both slots are disabled upon power-up, i.e., all supply outputs are off. in response to an overcurrent fault condition, writing a logical 1 back into the active (or set) bit position will clear the bit and deassert /int. the status of the /faultb pin is not affected by reading the status register or by clearing active status bits. notes: 1. if faultb has been set by an overcurrent condition on one or more of the main outputs, the onb input must go low to reset faultb. if faultb has been set by a vauxb overcurrent event, the auxenb input must go low to reset faultb. if an overcurrent has occurred on both a main output and the vaux output of slot b, both onb and auxenb of the slot must go low to reset faultb. 2. neither the faultb bits nor the /faultb pins are active when the mic2592b power paths are controlled by the system management interface. when using smi power path control, the auxenb and onb pins for that slot must be tied to gnd. 3:. if /force_onb is asserted (low), the /faultb pin will be unconditionally forced to its open-drain state. note, though, that the value in the faultb bit(s) function operation faultb fault pin status - slot b 1 = fault pin asserted (/faultb pin is low) 0 = fault pin deasserted (/faultb pin is high) see notes 1, 2, and 3. mainb main enable status - slot b represents the actual state (on/off) of the four main power outputs for slot b (+12v and +3.3v) 1 = main power on 0 = main power off vauxb vaux enable status - slot b represents the actual state (on/off) of the auxiliary power output for slot b 1 = aux power on 0 = aux power off vauxbf overcurrent fault: vauxb supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vbf overcurrent fault: +12v supply 1 = fault 0 = no fault d[1] reserved always read as zero 3vbf overcurrent fault: 3.3v supply 1 = fault 0 = no fault bit(s) function operation faultb fault pin status - slot b 1 = fault pin asserted (/faultb pin is low) 0 = fault pin deasserted (/faultb pin is high) see notes 1, 2, and 3. mainb main enable status - slot b represents the actual state (on/off) of the four main power outputs for slot b (+12v and +3.3v) 1 = main power on 0 = main power off vauxb vaux enable status - slot b represents the actual state (on/off) of the auxiliary power output for slot b 1 = aux power on 0 = aux power off vauxbf overcurrent fault: vauxb supply 1 = fault 0 = no fault d[3] reserved always read as zero 12vbf overcurrent fault: +12v supply 1 = fault 0 = no fault d[1] reserved always read as zero 3vbf overcurrent fault: 3.3v supply 1 = fault 0 = no fault d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-only read-only read-only read/write read-only read/write read-only read/write faultb mainb vauxb vauxbf reserved 12vbf reserved 3vbf
mic2592b micrel march 2005 26 m9999-033105 common status register (cs) 8-bits, read/write common status register (cs) d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved bit(s) function operation d[7] reserved always read as zero d[6] reserved always read as zero gpi_b0 general purpose input 0, slot b state of gpi_b0 pin gpi_a0 general purpose input 0, slot a state of gpi_a0 pin intmsk interrupt mask 0 = /int generation is enabled 1 = /int generation is disabled. the mic2592b does not participate in the smbus alert response address (ara) protocol uv_int undervoltage interrupt 0 = no uvlo fault 1 = uvlo fault set whenever a circuit breaker fault condition occurs as a result of an undervoltage lockout condition on one of the main supply inputs. this bit is only set if a uvlo condition occurs while the on[a/b] pin is asserted or the main[a/b] control bits are set ot_int overtemperature interrupt 0 = die temp < 160c. 1 = fault: die temp > 160c. set if a fault occurs as a result of the mic2592bs die temperature exceeding 160c d[0] reserved unde? ned power-up default value: 00000000b = 00h command_byte value (r/w): 00000110b = 06h bit(s) function operation d[7] reserved always read as zero d[6] reserved always read as zero gpi_b0 general purpose input 0, slot b state of gpi_b0 pin gpi_a0 general purpose input 0, slot a state of gpi_a0 pin intmsk interrupt mask 0 = /int generation is enabled 1 = /int generation is disabled. the mic2592b does not participate in the smbus alert response address (ara) protocol uv_int undervoltage interrupt 0 = no uvlo fault 1 = uvlo fault set whenever a circuit breaker fault condition occurs as a result of an undervoltage lockout condition on one of the main supply inputs. this bit is only set if a uvlo condition occurs while the on[a/b] pin is asserted or the main[a/b] control bits are set ot_int overtemperature interrupt 0 = die temp < 160c. 1 = fault: die temp > 160c. set if a fault occurs as a result of the mic2592bs die temperature exceeding 160c d[0] reserved unde? ned bit(s) function operation d[7] reserved always read as zero d[6] reserved always read as zero gpi_b0 general purpose input 0, slot b state of gpi_b0 pin gpi_a0 general purpose input 0, slot a state of gpi_a0 pin intmsk interrupt mask 0 = /int generation is enabled 1 = /int generation is disabled. the mic2592b does not participate in the smbus alert response address (ara) protocol uv_int undervoltage interrupt 0 = no uvlo fault 1 = uvlo fault set whenever a circuit breaker fault condition occurs as a result of an undervoltage lockout condition on one of the main supply inputs. this bit is only set if a uvlo condition occurs while the on[a/b] pin is asserted or the main[a/b] control bits are set ot_int overtemperature interrupt 0 = die temp < 160c. 1 = fault: die temp > 160c. set if a fault occurs as a result of the mic2592bs die temperature exceeding 160c d[0] reserved unde? ned d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] read-write read-write read-only read-only read-write read-write read-write read-only reserved reserved gpi_b0 gpi_a0 intmsk uv_int ot_int reserved
march 2005 27 m9999-033105 mic2592b micrel applications information sense resistor selection the 12v and the 3.3v supplies employ internal current sens- ing circuitry to detect overcurrent conditions that may trip the circuit breaker. an external sense resistor is used to monitor the current that passes through the external mosfet for each slot of the 12v and 3.3v rails. the sense resistor is nominally valued at: r sense(nom) = v thilimit i limit where v thilimit is the typical (or nominal) circuit breaker thilimit is the typical (or nominal) circuit breaker thilimit threshold voltage (50mv) and i limit is the nominal inrush limit is the nominal inrush limit load current level to trip the internal circuit breaker. to accommodate worse-case tolerances in the sense re- sistor (for a 1% initial tolerance, allow 3% tolerance for variations over time and temperature) and circuit breaker threshold voltages, a slightly more detailed calculation must be used to determine the minimum and maximum hot swap load currents. as the mic2592bs minimum current limit threshold voltage is 45mv, the minimum hot swap load current is determined where the sense resistor is 3% high: i limit(min) = = 45mv (1.03 r sense(nom) ) 43.7mv r sense(nom) keep in mind that the minimum hot swap load current should be greater than the application circuits upper steady-state load current boundary. once the lower value of r sense has been calculated, it is good practice to check the maximum hot swap load current (i limit(max) ) which the circuit may let pass in the case of tolerance build-up in the opposite limit(max) let pass in the case of tolerance build-up in the opposite limit(max) direction. here, the worse-case maximum is found using a v thilimit(max) threshold of 55mv and a sense resistor 3% low in value: thilimit(max) low in value: thilimit(max) i limit(max) = = 55mv (0.97 r sense(nom) ) 56.7mv r sense(nom) in this case, the application circuits must be sturdy enough to operate up to approximately 1.25x the steady-state hot swap load currents. for example, if one of the 12v slots of the mic2592b circuit must pass a minimum hot swap load current of 1.5a without nuisance trips, r sense should be set to: r sense(nom) = = 30m 45mv 1.5a where the nearest 1% standard value is 30.1m?. at the other tolerance extremes, i limit(max) for the circuit in question is then simply: i limit(max) = = 1.88a 56.7mv 30.1m with a knowledge of the application circuits maximum hot swap load current, the power dissipation rating of the sense resistor can be determined using p = i 2 r. here, the current is i limit(max) = 1.88a and the resistance r sense(max) = (1.03)(r limit(max) (1.03)(r limit(max) sense(nom) ) = 31.00m?. thus, the sense resistors sense(max) ) = 31.00m?. thus, the sense resistor s sense(max) maximum power dissipation is: sense(nom) maximum power dissipation is: sense(nom) p max = (1.88a) 2 x (31.00m?) = 0.110w a 0.25w sense resistor is a good choice in this application. pcb layout suggestions and hints 4-wire kelvin sensing because of the low value required for the sense resistor, special care must be used to accurately measure the volt- age drop across it. speci? cally, the measurement technique across r sense must employ 4-wire kelvin sensing. this is simply a means of ensuring that any voltage drops in the power traces connected to the resistors are not picked up by the signal conductors measuring the voltages across the sense resistors. figure 13 illustrates how to implement 4-wire kelvin sensing. as the ? gure shows, all the high current in the circuit (from v in through r sense and then to the drain of the n-channel power mosfet) ? ows directly through the power pcb traces and through r sense . the voltage drop across r sense is sampled in such a way that the high currents through the power traces will not introduce signi? cant parasitic voltage drops in the sense leads. it is recommended to connect the hot swap controllers sense leads directly to the sense resistors metalized contact pads. the kelvin sense signal traces should be symmetrical with equal length and width, kept as short as possible, and isolated from any noisy signals and planes. additionally, for designs that implement kelvin sense con- nections that exceed 1" in length and/or if the kelvin (signal) traces are vulnerable to noise possibly being injected onto these signals, the example circuit shown in figure 14 can be implemented to combat noisy environments. this circuit implements a 1.6 mhz low-pass ? lter to attenuate higher frequency disturbances on the current sensing circuitry. however, individual system analysis should be used to de- termine if ? ltering is necessary and to select the appropriate cutoff frequency for each speci? c application. other layout considerations figure 15 is a suggested pcb layout diagram for the mic2592b power traces, kelvin sense connections, and capacitor com- ponents. in this illustration, only the 12v slot b is shown but a similar approach is suggested for both slots of each main power rail (12v and 3.3v). many hot swap applications will require load currents of several amperes. therefore, the power (12vin and return, 3vin and return) trace widths (w) need to be wide enough to allow the current to ? ow while the rise in temperature for a given copper plate (e.g., 1oz. or 2oz.) is kept to a maximum of 10c to 25c. the return (or power ground) trace should be the same width as the positive voltage power traces (input/load) and isolated from any ground and signal planes so that the controllers power is common mode. also, these traces should be as short as possible in order to minimize the ir drops between the input and the load. as indicated in the pin description section, an external connection must be made that ties together both channel inputs ((+) kelvin sense) of each main power rail (i.e., 3vina and 3vinb, 12vina and 12vinb must be externally connected). these connections should be implemented di- rectly at the chip. insure that the voltage drop between the two (+) kelvin sense inputs for each rail is no greater than 0.2mv by using a common power path for the two inputs
mic2592b micrel march 2005 28 m9999-033105 (e.g., 12vina, 12vinb). finally, the use of plated-through vias will be necessary to make circuit connection to the power, ground, and signal planes on multi-layer pcbs. r sense power trace from v in pcb track width: 0.03" per ampere using 1oz cu power trace to mosfet drain signal trace to mic2592b vin pin signal trace to mic2592b sense pin note: each sense lead trace shall be balanced for best performance & equal length/equal aspect ratio. r sense metalized contact pads figure 13. 4-wire kelvin sense connections for r sense sense vin 1k? r sense mic2592b controller 100pf high-current power traces to the external mosfet and load to the input power supply figure 14. current limit sense filter for noisy sys- tems
march 2005 29 m9999-033105 mic2592b micrel *power mosfet (so-8) *sense resistor w w current flow to the load current flow to the load w current flow from the load via to gnd plane via to signal plane (gate pin connection) **r4 15 **c gs **c miller - drawing is not to scale and not all pins shown for clarity- *see table 4 for part numbers and vendors **optional components ***recommended components (variable in value, see functional description and applications information) trace width (w) guidelines given in "pcb layout recommendations" section of the datasheet 12v(slot b) is illustrated in this example. a similar layout is suggested for the 3v supply and both slots mic2592b 25 26 27 28 30 31 32 17 3vinb cfilterb /pwrgd /faultb gnd gnd vstbyb 12voutb /force_onb n/c 12vgateb 12vsenseb 12vinb c1 0.1f 33 36 34 35 29 d d d d via to signal plane (gate pin connection) via to gnd plane ***c filter s s s g figure 15. suggested pcb layout for sense resistor , power mosfet , and capacitors
mic2592b micrel march 2005 30 m9999-033105 mosfet and sense resistor vendors device types, part numbers, and manufacturer contact infor- mation for power mosfets and sense resistors are provided in table 4. some of the recommended mosfets include a metal (tab) heat sink on the bottom side of the package. contact the device manufacturer for package information. key power mosfet type(s) mosfet vendors n-channel p-channel package contact information vishay - siliconix si4420dy si4435bdy so-8 www.siliconix.com si4442dy si4427bdy so-8 (203) 452-5664 si3442dv si4405dy so-8 si4410dy si4425bdy so-8 si7860adp si7483adp powerpak so-8 si7344dp si7491dp powerpak so-8 si7844dp (dual) si7945dp (dual) powerpak so-8 si7114dn si7423dn 1212 so-8 si7806adn si7421dn 1212 so-8 international recti? er irf7882 irf7424 so-8 www.irf.com irf7413 irf7416 so-8 (310) 322-3331 irf7313 (dual) irf7328 (dual) so-8 resistor vendors sense resistors contact information vishay - dale wsl and wsr series www.vishay.com/docswsl_30100.pdf (203) 452-5664 irc oars series www.irctt.com/pdf_? les/oars.pdf lr series www.irctt.com/pdf_? les/lrc.pdf second source to wsl (828) 264-8861 table 4. mosfet and sense resistor vendors mosfet vendors n-channel p-channel package contact information vishay - siliconix si4420dy si4435bdy so-8 www.siliconix.com si4442dy si4427bdy so-8 (203) 452-5664 si3442dv si4405dy so-8 si4410dy si4425bdy so-8 si7860adp si7483adp powerpak so-8 si7344dp si7491dp powerpak so-8 si7844dp (dual) si7945dp (dual) powerpak so-8 si7114dn si7423dn 1212 so-8 si7806adn si7421dn 1212 so-8 irf7413 irf7313 (dual) irf7328 (dual) so-8 mosfet vendors n-channel p-channel package contact information vishay - siliconix si4420dy si4435bdy so-8 www.siliconix.com si4442dy si4427bdy so-8 (203) 452-5664 si3442dv si4405dy so-8 si4410dy si4425bdy so-8 si7860adp si7483adp powerpak so-8 si7344dp si7491dp powerpak so-8 si7844dp (dual) si7945dp (dual) powerpak so-8 si7114dn si7423dn 1212 so-8 si7806adn si7421dn 1212 so-8 irf7424 so-8 www.irf.com irf7416 so-8 (310) 322-3331 irf7313 (dual) irf7328 (dual) so-8 mosfet vendors n-channel p-channel package contact information vishay - siliconix si4420dy si4435bdy so-8 www.siliconix.com si4442dy si4427bdy so-8 (203) 452-5664 si3442dv si4405dy so-8 si4410dy si4425bdy so-8 si7860adp si7483adp powerpak so-8 si7344dp si7491dp powerpak so-8 si7844dp (dual) si7945dp (dual) powerpak so-8 si7114dn si7423dn 1212 so-8 si7806adn si7421dn 1212 so-8 irf7424 so-8 www.irf.com irf7416 so-8 (310) 322-3331 irf7313 (dual) irf7328 (dual) so-8 mosfet vendors n-channel p-channel package contact information vishay - siliconix si4420dy si4435bdy so-8 www.siliconix.com si4442dy si4427bdy so-8 (203) 452-5664 irf7424 so-8 www.irf.com irf7416 so-8 (310) 322-3331 resistor vendors sense resistors contact information (203) 452-5664 irc oars series www.irctt.com/pdf_? les/oars.pdf lr series www.irctt.com/pdf_? les/lrc.pdf second source to wsl (828) 264-8861 resistor vendors sense resistors contact information vishay - dale wsl and wsr series www.vishay.com/docswsl_30100.pdf (203) 452-5664 irc oars series www.irctt.com/pdf_? les/oars.pdf lr series www.irctt.com/pdf_? les/lrc.pdf second source to wsl (828) 264-8861 resistor vendors sense resistors contact information vishay - dale wsl and wsr series www.vishay.com/docswsl_30100.pdf (203) 452-5664 irc oars series www.irctt.com/pdf_? les/oars.pdf lr series www.irctt.com/pdf_? les/lrc.pdf second source to wsl (828) 264-8861
mic2592b micrel march 2005 31 m9999-033105 package information 48-pin tqfp micrel, inc. 1849 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however , no responsibility is assumed by micrel for its use. micrel reserves the right to change circuitry and speci? cations at any time without noti? cation to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signi? cant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is at purchaser s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2004 micrel, incorporated.

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